鏅傞枔锛�2025/4/29 18:27:33
闁辫畝锛�29
EP4SGX180FF35I3G 鏄� Altera锛堢従(xi脿n)鐐� Intel FPGA锛夊叕鍙哥敓鐢�(ch菐n)鐨� Stratix IV GX 绯诲垪 FPGA 鑺墖銆傝┎绯诲垪鑺墖灏堢偤楂樻�ц兘銆佷綆鍔熻�楁噳鐢ㄨō瑷堬紝閬╃敤浜庨�氫俊鍩虹瑷柦銆佸唬鎾闋昏檿鐞�銆侀珮绱氭垚鍍忓拰娓│娓噺绛夐牁鍩�銆�
銆�銆�Stratix IV GX 绯诲垪闆嗘垚浜嗚睈瀵岀殑鏁�(sh霉)瀛椾俊铏熻檿鐞� (DSP) 妯″銆佸祵鍏ュ紡瀛樺劜鍣ㄤ互鍙婇珮閫熶覆琛屾敹鐧�(f膩)鍣�銆侲P4SGX180FF35I3G 鐗瑰垾閬╁悎闇�瑕侀珮閭忚集瀵嗗害鍜屽京闆滅郴绲�(t菕ng)闆嗘垚鐨勬噳鐢ㄥ牬鏅�銆�
鍨嬭櫉锛欵P4SGX180FF35I3G
銆�銆�灏佽椤炲瀷锛欶BGA 1196
銆�銆�鏍稿績闆诲锛�0.9V
銆�銆�I/O 闆诲锛�1.5V 鎴� 1.8V
銆�銆�閭忚集鍠厓鏁�(sh霉)閲忥細绱� 180K
銆�銆�瀛樺劜鍣ㄨ硣婧愶細绱� 12.6 Mb 宓屽叆寮忓瓨鍎插櫒
銆�銆�DSP 妯″鏁�(sh霉)閲忥細360
銆�銆�鏀剁櫦(f膩)鍣ㄩ�氶亾鏁�(sh霉)閲忥細24
銆�銆�鏈�澶у伐浣滈牷鐜囷細楂橀仈 600 MHz
銆�銆�婧害鑼冨湇锛氬伐妤�(y猫)绱氾紙-40掳C 鑷� +85掳C锛�
EP4SGX180FF35I3G 鎻愪緵浜嗗崜瓒婄殑鎬ц兘鍜岄潏娲绘��锛屽叾涓昏鐗规�у寘鎷細
銆�銆�1. 楂橀倧杓瘑搴︼細鏀寔澶氶仈 180K 鐨勯倧杓柈鍏�锛岃兘澶犲鐝�(xi脿n)寰╅洔鐨勬暩(sh霉)瀛楅浕璺ō瑷�銆�
銆�銆�2. 寮峰ぇ鐨� DSP 鍔熻兘锛氬収缃� 360 鍊嬪皥鐢� DSP 妯″锛岄仼鍚堟诞榛為亱绠�銆佹烤娉㈠櫒瑷▓鍜屽叾浠栬▓绠楀瘑闆嗗瀷浠诲嫏銆�
銆�銆�3. 楂橀�熶覆琛屾敹鐧�(f膩)鍣細鎻愪緵 24 鍊嬮珮閫熸敹鐧�(f膩)鍣ㄩ�氶亾锛屾暩(sh霉)鎿�(j霉)閫熺巼楂橀仈 11.3 Gbps锛屾敮鎸� PCIe銆乆AUI 鍜� CPRI 绛夊崝(xi茅)璀�銆�
銆�銆�4. 澶у閲忓祵鍏ュ紡瀛樺劜鍣細闆嗘垚绱� 12.6Mb 鐨� RAM 璩囨簮锛屾笡灏戝皪澶栭儴瀛樺劜鐨勯渶姹�銆�
銆�銆�5. 闈堟椿鐨� I/O 妯欐簴鏀寔锛氬吋瀹瑰绋� I/O 妯欐簴锛屽 LVDS銆丠STL 鍜� SSTL銆�
銆�銆�6. 鍙潬鎬ц垏浣庡姛鑰楋細閲囩敤鍏堥�茬殑宸ヨ棟鎶�琛擄紝鍦ㄤ繚璀夋�ц兘鐨勫悓鏅傞檷浣庡姛鑰�銆�
銆�銆�7. 寤ｆ硾鐨勯枊鐧�(f膩)宸ュ叿鏀寔锛氶�氶亷 Quartus II 杌熶欢鎻愪緵瀹屾暣鐨勯枊鐧�(f膩)鐠�(hu谩n)澧冿紝绨″寲瑷▓娴佺▼銆�
EP4SGX180FF35I3G 寤ｆ硾鎳夌敤浜庝互涓嬮牁鍩燂細
銆�銆�1. 閫氫俊瑷倷锛氬寘鎷劇绶氬熀绔欍�佽矾鐢卞櫒銆佷氦鎻涙绛�锛岀敤浜庢暩(sh霉)鎿�(j霉)鍖呰檿鐞嗗拰淇¤櫉瑾垮埗瑙ｈ銆�
銆�銆�2. 寤ｆ挱瑕栭牷铏曠悊锛氭敮鎸佸鏅傝闋荤法纰�銆佽В纰煎拰鍦栧儚澧炲挤鍔熻兘銆�
銆�銆�3. 楂樻�ц兘瑷堢畻锛氬彲鐢ㄤ簬鍔犻�熸湇鍕欏櫒涓殑绉戝瑷堢畻浠诲嫏銆�
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銆�銆�5. 閱�(y墨)鐧傛垚鍍忥細瀵︾従(xi脿n)瓒呰伈娉�銆丆T 鍜� MRI 瑷倷涓殑鍦栧儚閲嶅缓绠楁硶銆�
銆�銆�6. 宸ユキ(y猫)鑷嫊鍖栵細鎺у埗绯荤当(t菕ng)鐨勫鏅傛暩(sh霉)鎿�(j霉)铏曠悊鑸囧崝(xi茅)璀拌綁鎻�銆�
銆�銆�瑭茶姱鐗囨啈鍊熷叾寮峰ぇ鐨勫姛鑳藉拰闈堟椿鐨勬灦妲�锛屾垚鐐鸿ū澶氶珮绔浕瀛愮郴绲�(t菕ng)鐨勭悊鎯抽伕鎿�銆�
EP4SGX230FF35I3G
銆�銆�EP4SGX280FF35I3G
