EP4SGX110HF35I3N 鏅傞枔锛�2023/8/1 11:18:57 闁辫畝锛�473

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鐢�(ch菐n)鍝佸瀷铏�	EP4SGX110HF35I3N
鎻忚堪	闆嗘垚闆昏矾FPGA 488 I/O 1152FBGA
鍒嗛	闆嗘垚闆昏矾(IC)锛屽祵鍏ュ紡-FPGA(鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄ｅ垪)
鍒堕€犲晢	鑻辩壒鐖�
绯诲垪	Stratix?IV GX
鎵撳寘	鎵樼洡
闆朵欢鐙€鎱�(t脿i)	閬庢檪鐨�
闆诲-闆绘簮	0.87V?0.93V
宸ヤ綔婧害	-40掳C?100掳C(TJ)
鍖呰/绠�	1152-BBGA锛孎(xi脿n)CBGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏寘瑁�	1152-FBGA(35x35)
鍩烘湰闆朵欢铏�	EP4SGX110

鐢�(ch菐n)鍝佸湒鐗�

EP4SGX110HF35I3N

瑕�(gu墨)鏍煎弮鏁�(sh霉)

鍙法绋嬮倧杓鍨�	鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄ｅ垪
绗﹀悎姝愮洘RoHS	鏄�
鐙€鎱�(t脿i)	杞�(zhu菐n)绉�
鏈€澶ф檪閻橀牷鐜�	717.0鍏嗚但
JESD-30浠ｇ⒓	S-PBGA-B1152
JESD-609浠ｇ⒓	1铏�
绺絉AM浣�	9793536
CLB鏁�(sh霉)閲�	42240.0
杓稿叆鏁�(sh霉)閲�	488.0
閭忚集鍠厓鏁�(sh霉)	105600.0
杓稿嚭鏁�(sh霉)閲�	488.0
绔瓙鏁�(sh霉)	1152
绲勭箶	42240 CLBS
宄板€煎洖娴佹韩搴�(鈩�)	245
闆绘簮	0.9,1.2 / 3,1.5,2.5
璩囨牸鐙€鎱�(t脿i)	涓嶅悎鏍�
搴ч珮	3.6姣背
瀛愰鍒�	鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄ｅ垪
闆绘簮闆诲妯�(bi膩o)绋�	0.9浼�
鏈€灏忎緵闆婚浕澹�	0.87浼�
鏈€澶ч浕婧愰浕澹�	0.93浼�
瀹夎椤炲瀷	琛ㄩ潰璨艰
鎶€琛�(sh霉)	CMOS
绲傜瀹屾垚	閷�/閵€/閵�(Sn / Ag / Cu)
绲傜琛ㄦ牸	鐞�
绔瓙闁撹窛	1.0姣背
绲傜浣嶇疆	搴曢儴
鏅傞枔@宄板€煎洖娴佹韩搴︽渶澶у€�(绉�)	40
闀峰害	35.0姣背
瀵害	35.0姣背
鍖呰涓婚珨鏉愭枡	濉戞枡/鐠�(hu谩n)姘фü鑴�
鍖呰浠ｇ⒓	BGA
鍖呰绛夋晥浠ｇ⒓	BGA1152,34X34,40
鍖呰褰㈢媭	寤ｅ牬
鍖呰褰㈠紡	缍�(w菐ng)鏍奸櫍鍒�
鍒堕€犲晢鍖呰瑾槑	鐒￠墰锛孎(xi脿n)BGA-1152

鐠�(hu谩n)澧冭垏鍑哄彛鍒嗛

鐒￠墰鐙€鎱�(t脿i)/RoHS鐙€鎱�(t脿i)	鐒￠墰/绗﹀悎RoHS
姘村垎鏁忔劅鎬ф按骞�(MSL)	3(168灏忔檪)

鐗归粸

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鍙法绋嬮浕婧愭妧琛�(sh霉)锛屽彲鍦ㄦ渶澶х▼搴﹂檷浣庡姛鑰楃殑鍚屾檪鏈€澶у寲瑷�(sh猫)鍌欐€ц兘
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楂橀€熸暩(sh霉)瀛椾俊铏熻檿鐞�(DSP)妯″锛屾渶楂樺彲閰嶇疆鐐�9 x 9浣�锛�12 x 12浣�锛�18 x 18浣嶅拰36 x 36浣嶅叏绮惧害涔樻硶鍣紝鏈€楂橀牷鐜囩偤600 MHz
鏀寔澶氶仈24鍊嬫ā濉婂寲I / O bank 涓婄殑楂橀€熷閮ㄥ瓨鍎插櫒鎺ュ彛锛屽寘鎷珼DR锛孌DR2锛孌DR3 SDRAM锛孯LDRAM II锛孮DR II鍜孮DR II + SRAM
鍏锋湁涓茶鍣�/瑙ｄ覆鍣�(SERDES)锛屽嫊鎱�(t脿i)鐩镐綅灏嶆簴(DPA)鍜宻oft-CDR闆昏矾鐨勯珮閫烲VDS I / O鏀寔锛屾暩(sh霉)鎿�(j霉)閫熺巼楂橀仈1.6 Gbps
鏀寔婧愬悓姝ョ附绶氭(bi膩o)婧�锛屽寘鎷琒GMII锛孏bE锛孲PI-4 闅庢2(POS-PHY绱氬垾4)锛孲FI-4.1锛孹SBI锛孶TOPIA IV锛孨PSI鍜孋SIX-L1
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