EP4SGX110HF35C3N 鏅�(sh铆)闁擄細2023/8/1 11:20:40 闁辫畝锛�1003

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鐢�(ch菐n)鍝佸瀷铏�(h脿o)	EP4SGX110HF35C3N
鎻忚堪	闆嗘垚闆昏矾FPGA 488 I/O 1152FBGA
鍒嗛	闆嗘垚闆昏矾(IC)锛屽祵鍏ュ紡-FPGA(鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄ｅ垪)
鍒堕€犲晢	鑻辩壒鐖�
绯诲垪	Stratix?IV GX
鎵撳寘	鎵樼洡
闆朵欢鐙€鎱�(t脿i)	閬庢檪(sh铆)鐨�
闆诲-闆绘簮	0.87V?0.93V
宸ヤ綔婧害	0掳C?85掳C(TJ)
鍖呰/绠�	1152-BBGA锛孎(xi脿n)CBGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏寘瑁�	1152-FBGA(35x35)
鍩烘湰闆朵欢铏�(h脿o)	EP4SGX110

鐢�(ch菐n)鍝佸湒鐗�

EP4SGX110HF35C3N

瑕�(gu墨)鏍煎弮鏁�(sh霉)

鍙法绋嬮倧杓鍨�	鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄ｅ垪
绗﹀悎姝愮洘RoHS	鏄�
鐙€鎱�(t脿i)	杞�(zhu菐n)绉�
鏈€澶ф檪(sh铆)閻橀牷鐜�	717.0鍏嗚但
JESD-30浠ｇ⒓	S-PBGA-B1152
JESD-609浠ｇ⒓	1铏�(h脿o)
绺絉AM浣�	9793536
CLB鏁�(sh霉)閲�	42240.0
杓稿叆鏁�(sh霉)閲�	488.0
閭忚集鍠厓鏁�(sh霉)	105600.0
杓稿嚭鏁�(sh霉)閲�	488.0
绔瓙鏁�(sh霉)	1152
鏈€浣庡伐浣滄韩搴�	0鈩�
鏈€楂樺伐浣滄韩搴�	85鈩�
绲勭箶	42240 CLBS
宄板€煎洖娴佹韩搴�(鈩�)	245
闆绘簮	0.9,1.2 / 3,1.5,2.5
璩囨牸鐙€鎱�(t脿i)	涓嶅悎鏍�
搴ч珮	3.6姣背
瀛愰鍒�	鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄ｅ垪
闆绘簮闆诲妯�(bi膩o)绋�	0.9浼�
鏈€灏忎緵闆婚浕澹�	0.87浼�
鏈€澶ч浕婧愰浕澹�	0.93浼�
瀹夎椤炲瀷	琛ㄩ潰璨艰
鎶€琛�(sh霉)	CMOS
婧害绛夌礆(j铆)	鍏朵粬
绲傜瀹屾垚	閷�/閵€/閵�(Sn / Ag / Cu)
绲傜琛ㄦ牸	鐞�
绔瓙闁撹窛	1.0姣背
绲傜浣嶇疆	搴曢儴
鏅�(sh铆)闁揁宄板€煎洖娴佹韩搴︽渶澶у€�(绉�)	40
闀峰害	35.0姣背
瀵害	35.0姣背
鍖呰涓婚珨鏉愭枡	濉戞枡/鐠�(hu谩n)姘фü鑴�
鍖呰浠ｇ⒓	BGA
鍖呰绛夋晥浠ｇ⒓	BGA1152,34X34,40
鍖呰褰㈢媭	寤ｅ牬
鍖呰褰㈠紡	缍�(w菐ng)鏍奸櫍鍒�
鍒堕€犲晢鍖呰瑾槑	鐒￠墰锛孎(xi脿n)BGA-1152

鐠�(hu谩n)澧冭垏鍑哄彛鍒嗛

鐒￠墰鐙€鎱�(t脿i)/RoHS鐙€鎱�(t脿i)	鐒￠墰/绗﹀悎RoHS
姘村垎鏁忔劅鎬ф按骞�(MSL)	3(168灏忔檪(sh铆))

鐗归粸(di菐n)

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姣忓€�(g猫)閫氶亾鐨勫吀鍨嬬墿鐞嗕粙璩�(zh矛)闄勪欢(PMA)鍔熻€楀垎鍒ョ偤3.125 Gbps鍜�100 mW锛�6.375 Gbps鏅�(sh铆)鐐�135 mW
Stratix IV E鍣ㄤ欢鐨勫紩鑵虫帓鍒楋紝鏃ㄥ湪鍏佽ū灏囪ō(sh猫)瑷�(j矛)寰濻tratix III 閬风Щ鍒癝tratix IV E锛岃€屽皪(du矛)PCB鐨勫奖闊挎渶灏�
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鍏锋湁宓屽叆寮廝CIe纭琁P妯″鐨勫畬鏁碢CIe鍗�(xi茅)璀拌В姹烘柟妗堬紝閫欎簺妯″瀵�(sh铆)鐝�(xi脿n)PHY-MAC灞�锛屾暩(sh霉)鎿�(j霉)閺堣矾灞ゅ拰浜嬪嫏(w霉)铏曠悊灞ゅ姛鑳�
7,370鑷�33,294 Kb鐨勫寮�(qi谩ng)鍨婽riMatrix瀛樺劜(ch菙)鍣�锛岀敱涓夌óRAM 濉婂ぇ灏忕祫鎴�锛屽彲瀵�(sh铆)鐝�(xi脿n)鐪熸鐨勯洐绔彛瀛樺劜(ch菙)鍣ㄥ拰FIFO绶╂矕鍗€(q奴)
鍏锋湁涓茶鍣�/瑙ｄ覆鍣�(SERDES)锛屽嫊(d貌ng)鎱�(t脿i)鐩镐綅灏�(du矛)婧�(zh菙n)(DPA)鍜宻oft-CDR闆昏矾鐨勯珮閫烲VDS I / O鏀寔锛屾暩(sh霉)鎿�(j霉)閫熺巼楂橀仈(d谩)1.6 Gbps
鏀寔婧愬悓姝ョ附绶氭(bi膩o)婧�(zh菙n)锛屽寘鎷琒GMII锛孏bE锛孲PI-4 闅庢2(POS-PHY绱�(j铆)鍒�4)锛孲FI-4.1锛孹SBI锛孶TOPIA IV锛孨PSI鍜孋SIX-L1
楂橀€熸暩(sh霉)瀛椾俊铏�(h脿o)铏曠悊(DSP)妯″锛屾渶楂樺彲閰嶇疆鐐�9 x 9浣�锛�12 x 12浣�锛�18 x 18浣嶅拰36 x 36浣嶅叏绮惧害涔樻硶鍣紝鏈€楂橀牷鐜囩偤600 MHz
鎸佸閬�(d谩)24鍊�(g猫)妯″鍖朓 / O bank 涓婄殑楂橀€熷閮ㄥ瓨鍎�(ch菙)鍣ㄦ帴鍙�锛屽寘鎷珼DR锛孌DR2锛孌DR3 SDRAM锛孯LDRAM II锛孮DR II鍜孮DR II + SRAM
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