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EP4S40G5H40I2 鏄� Altera锛堢従(xi脿n)鐐� Intel FPGA锛夋帹鍑虹殑涓€娆惧熀浜� Stratix IV 绯诲垪鐨勯珮鎬ц兘 FPGA 鑺墖銆傝┎鑺墖閲囩敤鍏堥€�(j矛n)鐨� 40nm 鍒剁▼宸ヨ棟锛岄泦鎴愪簡澶ч噺鐨勯倧杓柈鍏�銆佹暩(sh霉)瀛椾俊铏�(h脿o)铏曠悊 (DSP) 妯″浠ュ強楂橀€熸敹鐧�(f膩)鍣紝閬╃敤浜庨€氫俊銆佽粛浜�銆佸伐妤�(y猫)鑷嫊(d貌ng)鍖栧強楂樻€ц兘瑷�(j矛)绠楃瓑闋�(l菒ng)鍩熴€�
銆€銆€Stratix IV 绯诲垪 FPGA 鐨勪富瑕佺壒榛�(di菐n)鍦ㄤ簬鍏堕珮瀵嗗害閭忚集璩囨簮銆侀潏娲荤殑 I/O 鏀寔浠ュ強寮�(qi谩ng)澶х殑宓屽叆寮忓瓨鍎�(ch菙)鍣ㄥ拰 DSP 鍔熻兘銆侲P4S40G5H40I2 鐗瑰垾閬╁悎闇€瑕佸京(f霉)闆滅畻娉曞(sh铆)鐝�(xi脿n)銆侀珮甯跺鏁�(sh霉)鎿�(j霉)鍌宠几鍜屼綆寤堕伈鎬ц兘鐨勬噳(y墨ng)鐢ㄥ牬鏅�銆�

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鍨嬭櫉(h脿o)锛欵P4S40G5H40I2
銆€銆€鍒剁▼宸ヨ棟锛�40nm
銆€銆€閭忚集鍠厓鏁�(sh霉)閲忥細绱� 40,176 ALMs
銆€銆€宓屽叆寮忓瓨鍎�(ch菙)鍣細鏈€澶� 13.8Mb
銆€銆€DSP 妯″锛氭渶澶� 680 鍊�(g猫) DSP 妯″
銆€銆€I/O 寮曡叧鏁�(sh霉)锛氭渶楂樻敮鎸� 912 鍊�(g猫)鐢ㄦ埗 I/O
銆€銆€鏀剁櫦(f膩)鍣ㄩ€熺巼锛氭渶楂樻敮鎸� 11.3 Gbps
銆€銆€鍔熻€楄寖鍦嶏細鏍规摎(j霉)鎳�(y墨ng)鐢ㄤ笉鍚岋紝鍕�(d貌ng)鎱�(t脿i)鍔熻€楅€氬父鍦ㄥ咕鐡﹀埌骞惧崄鐡︿箣闁�
銆€銆€灏佽椤炲瀷锛欶BGA-1168

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EP4S40G5H40I2 鍏锋湁浠ヤ笅椤憲鐗规€э細
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