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鍨嬭櫉锛欵P4S40G5H40C1N
銆€銆€绯诲垪锛歋tratix IV
銆€銆€宸ヨ棟绡€(ji茅)榛烇細40nm
銆€銆€閭忚集鍠厓鏁�(sh霉)閲忥細绱� 40,192 ALMs (Adaptive Logic Modules)
銆€銆€RAM 璩囨簮锛歁9K 濉� RAM 鏁�(sh霉)閲忕偤 876锛岀附瀛樺劜瀹归噺绱勭偤 7.9 Mb
銆€銆€DSP 妯″锛�360 鍊� DSP 濉�
銆€銆€閰嶇疆妯″紡锛氫富鍕曚覆琛� (AS)銆佽鍕曚覆琛� (PS) 鍜� JTAG
銆€銆€I/O 寮曡叧鏁�(sh霉)锛�684
銆€銆€宸ヤ綔婧害鑼冨湇锛�-40掳C 鑷� +85掳C
銆€銆€灏佽椤炲瀷锛欶BGA 1196
銆€銆€渚涢浕闆诲锛氬収(n猫i)鏍搁浕澹� 1.0V锛岃紨鍔╅浕婧� 2.5V/3.3V

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銆€銆€1. 楂樻€ц兘鏋舵(g貌u)锛氬熀浜� Stratix IV 骞宠嚭锛屾彁渚涢珮鏁堢殑鏅傞悩绠＄悊鍜屼綆寤堕伈鐨勫収(n猫i)閮ㄤ簰鑱�(li谩n)绲�(ji茅)妲�(g貌u)銆�
銆€銆€2. 澶у閲忛倧杓硣婧愶細鍖呭惈瓒呴亷 4 钀€嬮倧杓柈鍏冿紝鏀寔寰�(f霉)闆滅殑鏁�(sh霉)瀛楅浕璺ō(sh猫)瑷�銆�
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銆€銆€4. 楂橀€熸敹鐧�(f膩)鍣細鏀寔楂橀仈 11.3 Gbps 鐨勪覆琛岄張璺€熺巼锛岄仼鐢ㄤ簬楂橀€熸暩(sh霉)鎿�(j霉)鍌宠几銆�
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