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鎮ㄥソ锛屾杩庝締鍒扮董搴浕瀛愬競鍫寸恫(w菐ng) 鐧婚寗 | 鍏嶈不(f猫i)娉ㄥ唺

鎮ㄦ墍鍦ㄧ殑浣嶇疆锛�闆诲瓙鍏冨櫒浠堕噰璩肩恫(w菐ng) > IC鐧剧 > EP4CE6F17I8LN

EP4CE6F17I8LN 鐧�(f膩)甯冩檪(sh铆)闁� 鏅�(sh铆)闁擄細2025/4/29 10:43:17 鏌ョ湅 闁辫畝锛�36

EP4CE6F17I8LN 鏄� Altera锛堢従(xi脿n)宸茶 Intel 鏀惰臣锛夋帹鍑虹殑 Cyclone IV 绯诲垪 FPGA 鑺墖涓殑涓�鍊�(g猫)鍨嬭櫉銆傝┎绯诲垪 FPGA 浠ュ叾楂樻�у児(ji脿)姣斿拰浣庡姛鑰楃壒鎬ц�岃仦鍚�锛岄仼鐢ㄤ簬娑堣不(f猫i)闆诲瓙銆佸伐妤�(y猫)鎺у埗銆侀�氫俊瑷�(sh猫)鍌欑瓑澶氱ó闋�(l菒ng)鍩�銆�
銆�銆�Cyclone IV 绯诲垪鍩轰簬 65nm 宸ヨ棟鎶�琛�(sh霉)鍒堕��锛屾彁渚涜睈瀵岀殑閭忚集璩囨簮銆佹暩(sh霉)瀛椾俊铏熻檿鐞� (DSP) 妯″銆佸祵鍏ュ紡瀛樺劜鍣ㄤ互鍙婂绋帴鍙ｉ伕闋�(xi脿ng)銆侲P4CE6F17I8LN 鍏烽珨灞簬 Cyclone IV E 绯诲垪锛屼富瑕侀潰鍚戜腑绔噳(y墨ng)鐢ㄥ競鍫�锛屾彁渚涗簡鍧囪　鐨勬�ц兘鍜屾垚鏈�銆�

鍙冩暩(sh霉)

鑺墖鍨嬭櫉锛欵P4CE6F17I8LN
銆�銆�绯诲垪锛欳yclone IV E
銆�銆�閭忚集鍠厓鏁�(sh霉)閲忥細6306
銆�銆�DSP 妯″鏁�(sh霉)閲忥細32
銆�銆�RAM 绺介噺锛�232.2Kb
銆�銆�I/O 鏁�(sh霉)閲忥細291
銆�銆�閰嶇疆妯″紡锛氫富鍕曚覆琛� (AS)锛岃鍕曚覆琛� (PS)锛孞TAG
銆�銆�宸ヤ綔婧害鑼冨湇锛�-40掳C 鑷� +85掳C
銆�銆�灏佽椤炲瀷锛欶BGA 484
銆�銆�鏍稿績闆诲锛�1.1V
銆�銆�IO 闆诲锛�1.5V / 1.8V / 2.5V / 3.3V

鐗规��

EP4CE6F17I8LN 鎻愪緵浜嗛潏娲荤殑瑷�(sh猫)瑷�(j矛)閬搁爡(xi脿ng)鍜屽劒(y艒u)鍖栫殑鍔熻兘妯″锛屼互涓嬫槸鍏朵富瑕佺壒鎬э細
銆�銆�1. 楂樻晥鐨勯倧杓祼(ji茅)妲�(g貌u)锛氶噰鐢� Stratix II 鏋舵(g貌u)琛嶇敓鐨� ALM锛圓daptive Logic Module锛夛紝姣忓��(g猫) ALM 鍙互瀵�(sh铆)鐝�(xi脿n)寰�(f霉)闆滅殑绲勫悎閭忚集鎴栧鍊�(g猫)瀵勫瓨鍣�銆�
銆�銆�2. 鍏�(n猫i)缃� DSP 鍔熻兘锛氬叿鍌欏皥鐢ㄧ殑涔樻硶绱姞妯″锛岄仼鍚堥��(j矛n)琛屾暩(sh霉)瀛椾俊铏熻檿鐞嗕换鍕�(w霉)銆�
銆�銆�3. 澶氭ǎ鍖栫殑瀛樺劜璩囨簮锛氬寘鍚垎甯冨紡 RAM 鍜屽 RAM锛屾豢瓒充笉鍚岄鍨嬬殑瀛樺劜闇�姹�銆�
銆�銆�4. 寮�(qi谩ng)澶х殑 I/O 鏀寔锛氭敮鎸佸绋(bi膩o)婧�(zh菙n)鎺ュ彛鍗�(xi茅)璀帮紝渚嬪 PCIe銆丏DR2/3銆丩VDS 绛�銆�
銆�銆�5. 浣庡姛鑰楄ō(sh猫)瑷�(j矛)锛氶�氶亷鍕曟厠(t脿i)鍔熻�楃鐞嗘妧琛�(sh霉)鍜屽彲绶ㄧ▼鐩镐綅閹栧畾鐠�(hu谩n) (PLL)锛屾笡灏戞暣楂旇兘鑰�銆�
銆�銆�6. 瀹夊叏鎬э細鎻愪緵 AES 鍔犲瘑鍔熻兘锛屼繚璀�(h霉)鐢ㄦ埗瑷�(sh猫)瑷�(j矛)鐨勭煡璀樼敘(ch菐n)娆�(qu谩n)銆�

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EP4CE6F17I8LN 寤ｆ硾鎳�(y墨ng)鐢ㄤ簬浠ヤ笅闋�(l菒ng)鍩燂細
銆�銆�1. 娑堣不(f猫i)闆诲瓙鐢�(ch菐n)鍝侊細濡傝闋昏檿鐞嗐�侀煶闋昏В纰�銆佸湒鍍忚瓨鍒ョ瓑銆�
銆�銆�2. 宸ユキ(y猫)鑷嫊鍖栵細鍖呮嫭閬�(y霉n)鍕曟帶鍒躲�佹暩(sh霉)鎿�(j霉)閲囬泦銆佸(sh铆)鏅�(sh铆)鐩�(ji膩n)娓郴绲�(t菕ng)绛夈��
銆�銆�3. 閫氫俊瑷�(sh猫)鍌欙細鐢ㄤ簬鍩哄付铏曠悊銆佷俊铏熻(di脿o)鍒惰В瑾�(di脿o)銆佺恫(w菐ng)绲�(lu貌)浜ゆ彌绛夊姛鑳�銆�
銆�銆�4. 閱�(y墨)鐧傚剙鍣細渚嬪瓒呰伈娉㈡垚鍍�銆佸績闆诲湒鍒嗘瀽绛夐渶瑕侀珮鎬ц兘瑷�(j矛)绠楃殑鎳�(y墨ng)鐢�銆�
銆�銆�5. 宓屽叆寮忕郴绲�(t菕ng)闁嬬櫦(f膩)锛氫綔鐐轰富鎺ц姱鐗囨垨鍗�(xi茅)铏曠悊鍣�锛屽煼(zh铆)琛岀壒瀹氱畻娉曟垨浠诲嫏(w霉)銆�

鏇夸唬鍨嬭櫉

EP4CE6E22I8N
銆�銆�EP4CE6Q24I8N
銆�銆�EP4CE6F23I7

ep4ce6f17i8ln鎺ㄨ枽渚涙噳(y墨ng)鍟� 鏇村>

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  • 渚涙噳(y墨ng)鍟�
  • 鏁�(sh霉)閲�
  • 寤犲晢
  • 灏佽/鎵硅櫉
  • 瑭㈠児(ji脿)

ep4ce6f17i8ln鍙冩暩(sh霉)

  • 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″Designing an IP Surveillance CameraThree Reasons to Use FPGA's in Industrial DesignsCyclone IV FPGA Family Overview
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  • 妯�(bi膩o)婧�(zh菙n)鍖呰90
  • 椤炲垾闆嗘垚闆昏矾 (IC)
  • 瀹跺涵宓屽叆寮� - FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪锛�
  • 绯诲垪CYCLONE® IV E
  • LAB/CLB鏁�(sh霉)392
  • 閭忚集鍏冧欢/鍠厓鏁�(sh霉)6272
  • RAM 浣嶇附瑷�(j矛)276480
  • 杓稿叆/杓稿嚭鏁�(sh霉)179
  • 闁�鏁�(sh霉)-
  • 闆绘簮闆诲0.97 V ~ 1.03 V
  • 瀹夎椤炲瀷琛ㄩ潰璨艰
  • 宸ヤ綔婧害-40°C ~ 100°C
  • 灏佽/澶栨256-BGA
  • 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�256-FBGA锛�17x17锛�
  • 鍏跺畠鍚嶇ū544-2651