EP3SL200H780I3 鏅傞枔锛�2025/4/27 17:23:38 闁辫畝锛�28

EP3SL200H780I3 鏄� Altera 鍏徃锛堢従(xi脿n)宸茶 Intel 鏀惰臣锛夋帹鍑虹殑 Stratix III 绯诲垪 FPGA 鑺墖涓殑涓€娆俱€傝┎绯诲垪鍣ㄤ欢灏堢偤楂樻€ц兘銆侀珮瀵嗗害鎳�(y墨ng)鐢ㄨō(sh猫)瑷堬紝寤ｆ硾鎳�(y墨ng)鐢ㄤ簬閫氫俊銆佸伐妤�(y猫)鑷嫊鍖�銆侀啱(y墨)鐧傛垚鍍忓拰瑕栭牷铏曠悊绛夐牁(l菒ng)鍩�銆侲P3SL200H780I3 鎻愪緵浜嗚睈瀵岀殑閭忚集璩囨簮銆佹暩(sh霉)瀛椾俊铏熻檿鐞� (DSP) 妯″浠ュ強楂橀€熶覆琛屾敹鐧�(f膩)鍣�锛岃兘澶犳豢瓒冲京(f霉)闆滅殑绯荤当(t菕ng)绱氶泦鎴愰渶姹�銆�
銆€銆€Stratix III 绯诲垪閲囩敤鍏堥€�(j矛n)鐨� 65nm 宸ヨ棟鍒堕€�锛屾敮鎸侀珮閬�(d谩) 11.3Gbps 鐨勪覆琛屾暩(sh霉)鎿�(j霉)閫熺巼锛屽苟涓斿叿鍌欓潏娲荤殑鏋舵(g貌u)锛屽彲閬╂噳(y墨ng)澶氱ó鎳�(y墨ng)鐢ㄩ渶姹�銆�

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鍨嬭櫉锛欵P3SL200H780I3
銆€銆€閭忚集鍠厓鏁�(sh霉)锛氱磩 200,000
銆€銆€宓屽叆寮忓瓨鍎插櫒瀹归噺锛�9.1 Mb
銆€銆€DSP 妯″鏁�(sh霉)閲忥細144
銆€銆€I/O 寮曡叧鏁�(sh霉)閲忥細780
銆€銆€閰嶇疆鏂瑰紡锛氫富鍕曚覆琛� (AS)銆佽鍕曚覆琛� (PS)銆丣TAG
銆€銆€宸ヤ綔婧害鑼冨湇锛�-40掳C 鑷� +85掳C
銆€銆€灏佽椤炲瀷锛欶BGA
銆€銆€鏍稿績闆诲锛�1.0V
銆€銆€I/O 闆诲锛�1.5V / 1.8V / 2.5V / 3.3V

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EP3SL200H780I3 鎻愪緵浜嗗挤(qi谩ng)澶х殑瑷堢畻鑳藉姏鍜岄珮搴﹂潏娲绘€�锛屽叾涓昏鐗规€у寘鎷細
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銆€銆€2. DSP 鍎�(y艒u)鍖栵細鍏�(n猫i)鍚� 144 鍊嬪皥鐢� DSP 妯″锛屾敮鎸侀珮鏁堢殑娴粸閬嬬畻鍙婃烤娉㈠姛鑳�銆�
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EP3SL200H780I3 鍦ㄥ鍊嬮牁(l菒ng)鍩熷叿鏈夊唬娉涙噳(y墨ng)鐢�锛屼緥濡傦細
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