鍨嬭櫉(h脿o)锛欵P3SL200F1152C2
銆�銆�绯诲垪锛歋tratix III
銆�銆�鍒堕�犲晢锛欰ltera (Intel FPGA)
銆�銆�灏佽�濓細FBGA 1152
銆�銆�I/O 鏁�(sh霉)閲忥細896
銆�銆�閭忚集鍠�鍏冩��(sh霉)閲忥細绱�200K
銆�銆�RAM 璩囨簮锛氱磩7.4 Mb
銆�銆�DSP 妯″�婃��(sh霉)閲忥細320
銆�銆�閰嶇疆闁冨瓨锛氫笉闆嗘垚澶栭儴閰嶇疆闁冨瓨
銆�銆�宸ヤ綔婧�搴﹁寖鍦嶏��-40掳C 鑷� +85掳C
銆�銆�宸ヨ棟绡�(ji茅)榛�(di菐n)锛�65nm
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EP3SL200F1152C2鍏峰倷浠ヤ笅涓昏�佺壒鎬э細
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EP3SL200F1152C2寤ｆ硾鎳�(y墨ng)鐢ㄤ簬浠ヤ笅闋�(l菒ng)鍩燂細
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EP3SL340H1152C2, EP3SL50F1152C2