鏅傞枔锛�2025/5/7 15:00:37
闁辫畝锛�20
EP3SL110F1152C3N 鏄� Altera 鍏徃锛堢従(xi脿n)鐐� Intel FPGA 閮ㄩ杸锛夋帹鍑虹殑 Stratix III 绯诲垪 FPGA 鑺墖涓殑涓�鍊嬪瀷铏�銆傝┎绯诲垪鑺墖閲囩敤 65nm 宸ヨ棟鎶�琛撳埗閫�锛屽叿鏈夐珮鎬ц兘閭忚集绲愭銆佽睈瀵岀殑宓屽叆寮忓瓨鍎插櫒鍜� DSP 妯″锛岄仼鐢ㄤ簬寰╅洔淇¤櫉铏曠悊銆侀�氫俊鍩虹瑷柦銆佽粛浜嬭埅绌虹瓑闋樺煙銆�
銆�銆�Stratix III 绯诲垪 FPGA 鎻愪緵浜嗗嚭鑹茬殑鎬ц兘鍜屼綆鍔熻�楃壒鎬э紝鑳藉婊胯冻楂樼鎳夌敤闇�姹�銆�
鍨嬭櫉锛欵P3SL110F1152C3N
銆�銆�鍝佺墝锛欰ltera (Intel FPGA)
銆�銆�绯诲垪锛歋tratix III
銆�銆�宸ヨ棟锛�65nm
銆�銆�閭忚集鍠厓鏁�(sh霉)閲忥細110K
銆�銆�RAM 绺介噺锛�8.4Mb
銆�銆�DSP 妯″鏁�(sh霉)閲忥細320
銆�銆�I/O 寮曡叧鏁�(sh霉)锛�576
銆�銆�閰嶇疆闁冨瓨锛氫笉鏀寔鍏�(n猫i)缃厤缃杻瀛�
銆�銆�宸ヤ綔婧害鑼冨湇锛�-40掳C 鑷� +85掳C
銆�銆�灏佽椤炲瀷锛欶BGA 1152
EP3SL110F1152C3N 灞簬 Stratix III 绯诲垪 FPGA锛屽叾涓昏鐗规�у寘鎷細
銆�銆�1. 楂樺瘑搴﹂倧杓硣婧愶細鎻愪緵澶氶仈 110K 鍊嬮倧杓柈鍏冿紝鍙鐝�(xi脿n)寰╅洔鐨勬暩(sh霉)瀛楅浕璺ō瑷�銆�
銆�銆�2. 澶у閲忓祵鍏ュ紡瀛樺劜鍣細鍖呭惈楂橀仈 8.4Mb 鐨� RAM 璩囨簮锛岄仼鍚堟暩(sh霉)鎿�(j霉)绶╁瓨鍜岀珐娌栧崁(q奴)鎳夌敤銆�
銆�銆�3. 楂樻晥鐨� DSP 鍔熻兘锛氶泦鎴愪簡 320 鍊嬪皥鐢� DSP 妯″锛屾敮鎸侀珮鎬ц兘鏁�(sh霉)瀛椾俊铏熻檿鐞�銆�
銆�銆�4. 鏀寔楂橀�熸帴鍙ｏ細鍏煎 PCIe銆丏DR2/3 鍏�(n猫i)瀛樻帴鍙ｄ互鍙婂绋覆琛屽崝(xi茅)璀�銆�
銆�銆�5. 浣庡姛鑰楁灦妲嬶細鍎�(y艒u)鍖栫殑 65nm 宸ヨ棟纰轰繚鍦ㄩ珮鎬ц兘閬嬭鏅備繚鎸佽純浣庣殑鍔熻�楁按骞�銆�
銆�銆�6. 鍙潬鎬ц垏闈堟椿鎬э細鏀寔鍕曟厠(t脿i)閲嶉厤缃姛鑳�锛屽厑瑷遍儴鍒嗗崁(q奴)鍩�?q奴)宕焤鏇存柊浠ラ仼鎳夊璁婄殑鎳夌敤闇�姹�銆�
銆�銆�7. 寤ｆ硾鐨勫伐浣滄韩搴﹁寖鍦嶏細鑳藉鍦ㄥ伐妤�(y猫)绱氭韩搴﹁寖鍦嶅収(n猫i)绌�(w臎n)瀹氶亱琛岋紝閬╂噳鍤磋嫑鐠�(hu谩n)澧�銆�
EP3SL110F1152C3N 甯哥敤浜庝互涓嬮牁鍩燂細
銆�銆�1. 閫氫俊绯荤当(t菕ng)锛氬鍩虹珯鏀剁櫦(f膩)淇℃銆佽矾鐢卞櫒鍜屼氦鎻涙绛夎ō鍌欎腑鐨勬牳蹇冧俊铏熻檿鐞嗘ā濉�銆�
銆�銆�2. 瑕栭牷铏曠悊锛氳闋荤法纰艰В纰�銆佸湒鍍忓寮�銆侀珮娓呴’绀虹瓑鍔熻兘銆�
銆�銆�3. 鏁�(sh霉)鎿�(j霉)涓績锛氬姞閫熸湇鍕欏櫒瑷堢畻浠诲嫏銆佺恫(w菐ng)绲″嵏杓夌瓑鍔熻兘銆�
銆�銆�4. 宸ユキ(y猫)鎺у埗锛氶亱鍕曟帶鍒�銆佽嚜鍕曞寲绯荤当(t菕ng)涓殑闂滈嵉绲勪欢銆�
銆�銆�5. 閱�(y墨)鐧傝ō鍌欙細鎴愬儚瑷倷銆佽ê鏂峰剙鍣ㄤ腑鐨勪俊铏熼噰闆嗚垏铏曠悊閮ㄥ垎銆�
銆�銆�6. 杌嶄簨鑸囪埅澶╋細闆烽仈绯荤当(t菕ng)銆佽(w猫i)鏄熼�氫俊銆佸皫鑸ō鍌欑瓑灏嶅彲闈犳�ц姹傛サ楂樼殑鍫村悎銆�
EP3SL200F1152C3N
銆�銆�EP3SL340F1152C3N
