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EP3SE80F780C4N 鏄� Altera 鍏徃锛堢従(xi脿n)宸茶 Intel 鏀惰臣锛夋帹鍑虹殑涓€娆� Stratix III 绯诲垪 FPGA 鑺墖銆傝┎绯诲垪鑺墖鍩轰簬 65nm 鍒堕€犲伐钘濓紝灏堢偤楂樻€ц兘銆侀珮瀵嗗害鎳�(y墨ng)鐢ㄨ€岃ō(sh猫)瑷�銆侲P3SE80F780C4N 鎿佹湁璞愬瘜鐨勯倧杓硣婧愩€佸祵鍏ュ紡瀛樺劜鍣ㄥ鍜屾暩(sh霉)瀛椾俊铏熻檿鐞� (DSP) 妯″锛岄仼鍚堢敤浜庨€氫俊鍩虹(ch菙)瑷�(sh猫)鏂姐€佸湒鍍忚檿鐞�銆佽闋昏檿鐞嗕互鍙婅粛浜嬪拰鑸┖鑸ぉ绛夐牁(l菒ng)鍩熺殑寰�(f霉)闆滅郴绲�(t菕ng)瑷�(sh猫)瑷�銆�
銆€銆€Stratix III 绯诲垪浠ュ叾鍗撹秺鐨勬€ц兘鍜岄潏娲绘€ц憲绋�锛岃兘澶犳豢瓒冲绋珮绔噳(y墨ng)鐢ㄩ渶姹傘€傝┎鍣ㄤ欢鏀寔楂橀€熶覆琛屾敹鐧�(f膩)鍣�锛屽叿鏈夐珮閬�(d谩) 6.375Gbps 鐨勬暩(sh霉)鎿�(j霉)鍌宠几閫熺巼锛岄仼鐢ㄤ簬闇€瑕佸ぇ閲忔暩(sh霉)鎿�(j霉)鍚炲悙鐨勬噳(y墨ng)鐢ㄥ牬鏅€�

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鍨嬭櫉锛欵P3SE80F780C4N
銆€銆€鍝佺墝锛欰ltera (Intel)
銆€銆€绯诲垪锛歋tratix III
銆€銆€鍒剁▼宸ヨ棟锛�65nm
銆€銆€閭忚集鍠厓鏁�(sh霉)锛氱磩 82,176
銆€銆€RAM 绺介噺锛氱磩 5.9Mb
銆€銆€DSP 妯″鏁�(sh霉)閲忥細360
銆€銆€I/O 寮曡叧鏁�(sh霉)锛�803
銆€銆€閰嶇疆闁冨瓨澶�?銆傜熬o鍏�(n猫i)缃杻瀛橈紝闇€澶栨帴閰嶇疆鑺墖
銆€銆€宸ヤ綔婧害鑼冨湇锛氬伐妤�(y猫)绱氾紙-40掳C 鑷� +85掳C锛�
銆€銆€灏佽褰㈠紡锛欶BGA1020

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EP3SE80F780C4N 鏄竴娆鹃珮搴﹂泦鎴愮殑 FPGA 鍣ㄤ欢锛屽叾涓昏鐗规€у寘鎷細
銆€銆€1. 楂樻€ц兘閭忚集绲�(ji茅)妲�(g貌u)锛氶噰鐢ㄩ珮鏁堢殑閭忚集鍠厓鏋舵(g貌u)锛屾敮鎸佸京(f霉)闆滅殑绲勫悎閭忚集鍜屾檪搴忛倧杓ō(sh猫)瑷�銆�
銆€銆€2. 鍏�(n猫i)缃ぇ瀹归噺 RAM锛氬叿鍌欏ぇ閲忕殑宓屽叆寮忓瓨鍎插櫒妯″锛屽彲鐢ㄤ簬瀵︾従(xi脿n) FIFO銆佺珐瀛樺拰鏌ユ壘琛ㄧ瓑鍔熻兘銆�
銆€銆€3. DSP 鍔熻兘寮峰ぇ锛氬寘鍚閬�(d谩) 360 鍊嬪皥鐢� DSP 妯″锛屾敮鎸佷箻娉曠疮鍔犻亱绠楀拰鍏朵粬鏁�(sh霉)瀛�(xu茅)鎿嶄綔锛岄潪甯搁仼鍚堟暩(sh霉)瀛椾俊铏熻檿鐞嗕换鍕�(w霉)銆�
銆€銆€4. 楂橀€熶覆琛屾敹鐧�(f膩)鍣細鏀寔楂橀仈(d谩) 6.375Gbps 鐨勬暩(sh霉)鎿�(j霉)閫熺巼锛屽彲鑸囧悇绋珮閫熸帴鍙ｇ劇绺€ｆ帴銆�
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銆€銆€7. 鍙潬鎬ч珮锛氱稉(j墨ng)閬庡毚(y谩n)鏍兼脯瑭�锛岄仼鐢ㄤ簬瑕佹眰鑻涘埢鐨勭挵(hu谩n)澧冿紝濡傝粛宸ュ拰鑸ぉ闋�(l菒ng)鍩�銆�

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EP3SE80F780C4N 寤ｆ硾鎳�(y墨ng)鐢ㄤ簬浠ヤ笅闋�(l菒ng)鍩燂細
銆€銆€1. 閫氫俊瑷�(sh猫)鍌欙細濡傚熀绔欍€佽矾鐢卞櫒鍜屼氦鎻涙(j墨)涓殑淇¤櫉铏曠悊鍜屽崝(xi茅)璀拌綁(zhu菐n)鎻�銆�
銆€銆€2. 瑕栭牷鍜屽湒鍍忚檿鐞嗭細渚嬪瀵︽檪瑕栭牷绶ㄧ⒓瑙ｇ⒓銆佸湒褰㈠姞閫熷拰鍦栧儚璀樺垾銆�
銆€銆€3. 宸ユキ(y猫)鑷嫊鍖栵細鐢ㄤ簬閬嬪嫊鎺у埗銆佹(j墨)鍣ㄨ瑕哄拰瀵︽檪鏁�(sh霉)鎿�(j霉)閲囬泦绯荤当(t菕ng)銆�
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