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EP3SE50F484I4 鏄敱 Altera锛堢従(xi脿n)宸茶 Intel 鏀惰臣锛夋帹鍑虹殑涓€娆惧熀浜� Stratix III 绯诲垪鐨� FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁€闄ｅ垪锛�銆傝┎鑺墖閬╃敤浜庨珮鎬ц兘瑷�(j矛)绠椼€侀€氫俊鍩虹(ch菙)瑷�(sh猫)鏂�銆佽粛浜嬪拰鑸┖鑸ぉ浠ュ強宸ユキ(y猫)鑷嫊鍖栫瓑闋�(l菒ng)鍩熴€侲P3SE50F484I4 鎻愪緵浜嗚睈瀵岀殑閭忚集璩囨簮銆佸祵鍏ュ紡瀛樺劜鍣ㄥ銆佹暩(sh霉)瀛椾俊铏熻檿鐞� (DSP) 妯″浠ュ強楂橀€熶覆琛屾敹鐧�(f膩)鍣�锛岃兘澶犳豢瓒冲京(f霉)闆滆ō(sh猫)瑷�(j矛)闇€姹�銆�
銆€銆€Stratix III 绯诲垪鏄� Altera 鐨勯珮绔� FPGA 绯诲垪涔嬩竴锛岄噰鐢� 65nm 鍒剁▼宸ヨ棟鍒堕€狅紝鍏峰倷寮�(qi谩ng)澶х殑鎬ц兘鍜屼綆鍔熻€楃壒鎬�銆�

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鍨嬭櫉锛欵P3SE50F484I4
銆€銆€绯诲垪锛歋tratix III
銆€銆€鍒剁▼宸ヨ棟锛�65nm
銆€銆€閭忚集鍠厓鏁�(sh霉)锛氱磩 50K
銆€銆€宓屽叆寮忓瓨鍎插櫒锛氭渶澶� 2.7 Mb
銆€銆€DSP 妯″锛�192 鍊�
銆€銆€I/O 寮曡叧鏁�(sh霉)锛�484
銆€銆€閰嶇疆妯″紡锛欰S/涓诲嫊涓茶銆佽鍕曚覆琛�銆丣TAG
銆€銆€宸ヤ綔闆诲锛氭牳蹇冮浕澹� 1.0V锛孖/O 闆诲鏀寔 1.5V/1.8V/2.5V/3.3V
銆€銆€灏佽椤炲瀷锛欶BGA锛團ine Pitch Ball Grid Array锛�
銆€銆€宸ヤ綔婧害鑼冨湇锛�-40掳C 鑷� +85掳C

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EP3SE50F484I4 鍏峰倷浠ヤ笅椤憲鐗规€э細
銆€銆€1. 楂樻€ц兘閭忚集鏋舵(g貌u)锛氬劒(y艒u)鍖栫殑鏌ユ壘琛� (LUT) 鍜岃Ц鐧�(f膩)鍣ㄧ祼(ji茅)妲�(g貌u)鎻愪緵楂樻晥鐨勯倧杓(sh铆)鐝�(xi脿n)銆�
銆€銆€2. 鍏�(n猫i)缃‖鏍� IP锛氬寘鎷� PCIe銆佷互澶恫(w菐ng) MAC 鍜屼笁閫熷崈鍏嗕粙璩�(zh矛)鐛�(d煤)绔嬫帴鍙ｇ瓑纭牳 IP 妯″銆�
銆€銆€3. 楂橀€熶覆琛屾敹鐧�(f膩)鍣細鏀寔楂橀仈(d谩) 6.375 Gbps 鐨勫偝杓搁€熺巼锛岄仼鍚堝厜绾栭€氫俊鍜岃儗鏉挎噳(y墨ng)鐢�銆�
銆€銆€4. 鏁�(sh霉)瀛椾俊铏熻檿鐞嗚兘鍔涳細192 鍊嬪皥鐢� DSP 妯″鏀寔寰�(f霉)闆滄暩(sh霉)瀛�(xu茅)閬�(y霉n)绠�锛屽 FFT銆佹烤娉㈠櫒瑷�(sh猫)瑷�(j矛)绛夈€�
銆€銆€5. 澶у閲忕墖涓婂瓨鍎插櫒锛氬収(n猫i)宓岃睈瀵岀殑 RAM 璩囨簮锛屾敮鎸佸垎甯冨紡瀛樺劜鍜屽瀛樺劜銆�
銆€銆€6. 鍙摯(ku貌)灞曟€э細鏀寔澶� FPGA 绱氳伅(li谩n)锛屾柟渚垮(sh铆)鐝�(xi脿n)鏇村ぇ瑕�(gu墨)妯＄殑瑷�(sh猫)瑷�(j矛)銆�
銆€銆€7. 宓屽叆寮忚(di脿o)瑭﹀伐鍏凤細閫氶亷 SignalTap II 閭忚集鍒嗘瀽鍎€閫�(j矛n)琛屽(sh铆)鏅備俊铏熺洠(ji膩n)娓拰瑾�(di脿o)瑭�銆�

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銆€銆€6. 楂樻€ц兘瑷�(j矛)绠楋細鐢ㄤ簬骞惰瑷�(j矛)绠椾换鍕�(w霉)鐨勫姞閫熷崱鎴栧崝(xi茅)铏曠悊鍣ㄦā濉�銆�