鏅傞枔锛�2023/8/1 11:05:10
闁辫畝锛�213
鐢�(ch菐n)鍝佸瀷铏� | EP3SE110F780C4N |
鎻忚堪 | 闆嗘垚闆昏矾FPGA 488 I/O 780FBGA |
鍒嗛 | 闆嗘垚闆昏矾(IC)锛屽祵鍏ュ紡-FPGA(鐝�(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪) |
鍒堕�犲晢 | 鑻辩壒鐖� |
绯诲垪 | Stratix?III E |
鎵撳寘 | 鎵樼洡 |
闆朵欢鐙�鎱�(t脿i) | 娲绘�� |
闆诲-闆绘簮 | 0.86V?1.15V |
宸ヤ綔婧害 | 0掳C?85掳C(TJ) |
鍖呰/绠� | 780-BBGA锛孎(xi脿n)CBGA |
渚涙噳鍟嗚ō鍌欏寘瑁� | 780-FBGA(29x29) |
鍩烘湰闆朵欢铏� | EP3SE110 |
EP3SE110F780C4N
鍙法绋嬮倧杓鍨� | 鐝�(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪 |
绗﹀悎姝愮洘RoHS | 鏄� |
鐙�鎱�(t脿i) | 杞夊叆 |
鏈�澶ф檪閻橀牷鐜� | 717.0鍏嗚但 |
JESD-30浠ｇ⒓ | S-PBGA-B780 |
JESD-609浠ｇ⒓ | 1铏� |
绺絉AM浣� | 8936448 |
杓稿叆鏁�(sh霉)閲� | 488.0 |
閭忚集鍠厓鏁�(sh霉) | 107500.0 |
杓稿嚭鏁�(sh霉)閲� | 488.0 |
绔瓙鏁�(sh霉) | 780 |
鏈�浣庡伐浣滄韩搴� | 0鈩� |
鏈�楂樺伐浣滄韩搴� | 85鈩� |
闆绘簮 | 1.2 / 3.3 |
璩囨牸鐙�鎱�(t脿i) | 涓嶅悎鏍� |
搴ч珮 | 3.5姣背 |
瀛愰鍒� | 鐝�(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪 |
闆绘簮闆诲妯欑ū | 0.9浼� |
鏈�灏忎緵闆婚浕澹� | 0.86浼� |
鏈�澶ч浕婧愰浕澹� | 0.94浼� |
瀹夎椤炲瀷 | 琛ㄩ潰璨艰 |
鎶�琛� | CMOS |
婧害绛夌礆 | 鍏朵粬 |
绲傜瀹屾垚 | 閷�/閵�/閵�(Sn / Ag / Cu) |
绲傜琛ㄦ牸 | 鐞� |
绔瓙闁撹窛 | 1.0姣背 |
绲傜浣嶇疆 | 搴曢儴 |
闀峰害 | 29.0姣背 |
瀵害 | 29.0姣背 |
闄勫姞鍔熻兘 | 瀹冧篃鍙互鍦�1.05鑷�1.15V鐨勯浕婧愯寖鍦嶅収(n猫i)宸ヤ綔 |
鍖呰涓婚珨鏉愭枡 | 濉戞枡/鐠�(hu谩n)姘фü鑴� |
鍖呰浠ｇ⒓ | BGA |
鍖呰绛夋晥浠ｇ⒓ | BGA780,28X28,40 |
鍖呰褰㈢媭 | 寤ｅ牬 |
鍖呰褰㈠紡 | 缍�(w菐ng)鏍奸櫍鍒� |
鍒堕�犲晢鍖呰瑾槑 | 鐒￠墰FBGA-780 |
鐒￠墰鐙�鎱�(t脿i)/RoHS鐙�鎱�(t脿i) | 鐒￠墰/绗﹀悎RoHS |
姘村垎鏁忔劅鎬ф按骞�(MSL) | 3(168灏忔檪) |
48,000鑷�338,000鍊嬬瓑鏁堥倧杓厓绱�(LE)
2,430鑷�20,497 Kbit鐨勫寮峰瀷TriMatrix瀛樺劜鍣�锛岀敱涓夌óRAM 濉婂ぇ灏忕祫鎴愶紝鍙鐝�(xi脿n)鐪熸鐨勯洐绔彛瀛樺劜鍣ㄥ拰FIFO绶╂矕鍗�(q奴)
楂橀�烡SP妯″鎻愪緵9脳9銆�12脳12銆�18脳18 鍜�36脳36涔樻硶鍣�(鏈�楂�550 MHz)锛屼箻娉曠疮鍔犲姛鑳藉拰鏈夐檺鑴堟矕闊挎噳(FIR)婵炬尝鍣ㄧ殑灏堢敤瀵︾従(xi脿n)
I / O锛欸ND锛歅WR姣旂巼鐐�8锛�1锛�1锛屽苟閫氶亷鐗囦笂鍜屽皝瑁濅笂鐨勫幓鑰﹀鐝�(xi脿n)浜嗗挤澶х殑淇¤櫉瀹屾暣鎬�
鍙法绋嬮浕婧愭妧琛擄紝鍙湪鏈�澶х▼搴﹂檷浣庡姛鑰楃殑鍚屾檪鏈�澶у寲瑷倷鎬ц兘
鍙伕鐨勬牳蹇冮浕澹�锛屽湪浣庡瑷倷涓彲鐢�(L瑷傝波浠ｇ⒓鍚庣洞)锛屽彲浠ラ伕鎿囨渶浣庡姛鐜囨垨鏈�楂樻�ц兘鐨勮ō鍌�
姣忓�嬭ō鍌欐渶澶�16鍊嬪叏灞�鏅傞悩锛�88鍊嬪崁(q奴)鍩熸檪閻樺拰116鍊嬪鍦嶆檪閻�
姣忓�嬭ō鍌欐渶澶�12鍊嬮帠鐩哥挵(hu谩n)(PLL)锛屾敮鎸丳LL閲嶉厤缃�锛屾檪閻樺垏鎻�锛屽彲绶ㄧ▼甯跺锛屾檪閻樺悎鎴愬拰鍕曟厠(t脿i)鐩哥Щ
鎵�鏈塈 / O bank鍧囧叿鏈夊皥鐢―QS閭忚集鐨勫収(n猫i)瀛樻帴鍙ｆ敮鎸�
鏀寔澶氶仈24鍊嬫ā濉婂寲I / O bank 涓婄殑楂橀�熷閮ㄥ瓨鍎插櫒鎺ュ彛锛屽寘鎷珼DR锛孌DR2锛孌DR3 SDRAM锛孯LDRAM II锛孮DR II鍜孮DR II + SRAM
澶氶仈1,104鍊嬬敤鎴禝 / O寮曡叧甯冪疆鍦�24鍊嬫ā濉婂寲I / O绲勪腑锛岄�欎簺妯″鏀寔寤ｆ硾鐨勮妤�(y猫)I / O妯欐簴
鍦ㄦ墍鏈塈 / O bank 涓婂叿鏈夎嚜鍕曟牎婧栨敮鎸佺殑鍕曟厠(t脿i)鐗囦笂绲傜(OCT)
鍏锋湁涓茶鍣�/瑙ｄ覆鍣�(SERDES)鍜屽嫊鎱�(t脿i)鐩镐綅灏嶆簴(DPA)闆昏矾鐨勯珮閫熷樊鍒咺 / O鏀寔锛屽彲瀵︾従(xi脿n)1.6 Gbps鐨勬�ц兘
鏀寔楂橀�熺恫(w菐ng)绲″拰閫氫俊绺界窔妯欐簴锛屽寘鎷琒PI-4.2锛孲FI-4锛孲GMII锛孶topia IV锛�10鍗冨厗浠ュお缍�(w菐ng)XSBI锛孯apid I / O鍜孨PSI
鍞竴鐨勯珮瀵嗗害锛岄珮鎬ц兘FPGA锛屾敮鎸�256浣岮ES 鏄撳け鎬у拰闈炴槗澶辨�у畨鍏ㄥ瘑閼帮紝浠ヤ繚璀疯ō瑷�
寮峰ぇ鐨勭墖涓婄啽鎻掓嫈鍜岄浕婧愭帓搴忔敮鎸�
闆嗘垚鐨勫惊鐠�(hu谩n)鍐椾綑鏍￠(CRC)锛岀敤浜庨厤缃瓨鍎插櫒閷妾㈡脯锛屽苟鍏锋湁鍤撮噸閷纰哄畾鍔熻兘锛屽彲鏀寔楂樺彲鐢ㄦ�х郴绲�(t菕ng)
鍏�(n猫i)缃尘閷法纰�(ECC)闆昏矾锛岀敤浜庢娓拰绯炬M144K TriMatrix瀛樺劜妯″涓殑鏁�(sh霉)鎿�(j霉)閷
Nios?II宓屽叆寮忚檿鐞嗗櫒鏀寔
鏀寔Altera?MegaCore? 鍔熻兘鍜孉ltera Megafunction鍚堜綔浼欎即瑷堝妰(AMPP SM)鐨勫鍊嬬煡璀樼敘(ch菐n)娆婂畯鍔熻兘
EP3SE110F780C4N绗﹁櫉
EP3SE110F780C4N鑵冲嵃
