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EP2SGX125GF1508C4G 鏄竴娆剧敱鑻辩壒鐖撅紙Intel锛夋帹鍑虹殑 Stratix II GX 绯诲垪 FPGA 鑺墖銆傝┎鑺墖灞簬楂樻�ц兘 FPGA锛屼富瑕侀潰鍚戦�氫俊銆佽▓绠�銆佷俊铏熻檿鐞嗗拰鍏朵粬闇�瑕侀珮閭忚集瀵嗗害鍜岄珮閫熶覆琛屾帴鍙ｇ殑鎳夌敤鍫存櫙銆係tratix II GX 绯诲垪鏀寔 PCI Express 鍜屽鍗冨厗浣嶆敹鐧�(f膩)鍣ㄥ姛鑳�锛岃兘澶犳豢瓒冲京闆滅郴绲�(t菕ng)瑷▓鐨勯渶姹�銆�
銆�銆�EP2SGX125GF1508C4G 鐨勬牳蹇冩槸鍩轰簬绗簩浠ｅ彲绶ㄧ▼閭忚集鏋舵锛屽叿鏈夎睈瀵岀殑閭忚集鍠厓銆佸祵鍏ュ紡瀛樺劜鍣ㄥ銆佹暩(sh霉)瀛椾俊铏熻檿鐞� (DSP) 妯″浠ュ強楂橀�熸敹鐧�(f膩)鍣�銆傚叾灏佽褰㈠紡鐐� FBGA锛團ine-Pitch Ball Grid Array锛�锛岄仼鍚堥珮寮曡叧鏁�(sh霉)鍜岄珮瀵嗗害鐨勯浕璺澘瑷▓銆�
鍨嬭櫉锛欵P2SGX125GF1508C4G
銆�銆�鍝佺墝锛欼ntel
銆�銆�绯诲垪锛歋tratix II GX
銆�銆�閭忚集鍠厓鏁�(sh霉)閲忥細绱� 125,000
銆�銆�鏈�澶х敤鎴� I/O 鏁�(sh霉)閲忥細569
銆�銆�閰嶇疆闁冨瓨锛氫笉闆嗘垚
銆�銆�鍏�(n猫i)閮� RAM锛氱磩 7.2 Mb
銆�銆�DSP 妯″鏁�(sh霉)閲忥細144
銆�銆�鏀剁櫦(f膩)鍣ㄩ�氶亾鏁�(sh霉)閲忥細24
銆�銆�鏀剁櫦(f膩)鍣ㄩ�熺巼鑼冨湇锛�375 Mbps 鑷� 6.375 Gbps
銆�銆�宸ヤ綔婧害鑼冨湇锛�-40掳C 鑷� +85掳C
銆�銆�渚涢浕闆诲锛�1.2V 鏍稿績闆诲锛�2.5V 閰嶇疆闆诲
銆�銆�灏佽椤炲瀷锛欶BGA
銆�銆�灏佽灏哄锛�35x35 mm
銆�銆�I/O 妯欐簴鏀寔锛歀VCMOS銆丩VDS銆丳CIe 绛�
EP2SGX125GF1508C4G 鍏锋湁浠ヤ笅闂滈嵉鐗规�э細
銆�銆�1. 楂樻�ц兘 FPGA 鏋舵锛氬熀浜庣浜屼唬 Stratix II GX 绯诲垪鏋舵锛屾彁渚涘挤澶х殑閭忚集铏曠悊鑳藉姏銆�
銆�銆�2. 闆嗘垚澶氬崈鍏嗕綅鏀剁櫦(f膩)鍣細鏀寔楂橀仈 6.375 Gbps 鐨勬暩(sh霉)鎿�(j霉)鍌宠几閫熺巼锛岄仼鐢ㄤ簬楂橀�熼�氫俊閺堣矾銆�
銆�銆�3. 宓屽叆寮忓瓨鍎插櫒璩囨簮锛氬寘鍚ぇ閲忓祵鍏ュ紡 RAM 妯″锛岀敤浜庡鐝�(xi脿n)寰╅洔鐨勬暩(sh霉)鎿�(j霉)绶╂矕鍜岃檿鐞嗗姛鑳姐��
銆�銆�4. DSP 妯″锛氬収(n猫i)鍚� 144 鍊嬪皥鐢� DSP 妯″锛屽彲浠ラ珮鏁堝煼(zh铆)琛屾诞榛為亱绠楀拰鍥哄畾榛為亱绠椼��
銆�銆�5. 澶氱ó I/O 妯欐簴鏀寔锛氬吋瀹� LVCMOS銆丩VDS 鍜� PCIe 绛夊绋婧�锛岄仼鎳夊唬娉涚殑鎳夌敤闇�姹傘��
銆�銆�6. 楂樺彲闈犳�э細閫氶亷鍤存牸鐨勮ō瑷堣垏娓│娴佺▼锛岀⒑淇濆湪宸ユキ(y猫)绱氭韩搴﹁寖鍦嶅収(n猫i)鐨勭┅(w臎n)瀹氶亱琛�銆�
銆�銆�7. 鏄撲簬闁嬬櫦(f膩)锛氭敮鎸� Quartus II 瑷▓杌熶欢锛屾彁渚涘叏闈㈢殑闁嬬櫦(f膩)宸ュ叿閺堜互绨″寲瑷▓娴佺▼銆�
EP2SGX125GF1508C4G 寤ｆ硾鎳夌敤浜庝互涓嬮牁鍩燂細
銆�銆�1. 閫氫俊瑷倷锛氬寘鎷矾鐢卞櫒銆佷氦鎻涙銆佸熀绔欐帶鍒跺櫒绛夐渶瑕侀珮閫熸暩(sh霉)鎿�(j霉)鍌宠几?sh霉)鑶遍紞鍟�?br>銆�銆�2. 瑷堢畻鍔犻�燂細浣滅偤鍗�(xi茅)铏曠悊鍣ㄦ垨鍔犻�熷紩鎿庯紝鐢ㄤ簬楂樻�ц兘瑷堢畻浠诲嫏銆�
銆�銆�3. 瑕栭牷铏曠悊锛氭敮鎸佸鏅傝闋荤法纰艰В纰�銆佸湒鍍忚檿鐞嗙瓑鍔熻兘銆�
銆�銆�4. 宸ユキ(y猫)鑷嫊鍖栵細鐢ㄤ簬鎺у埗绯荤当(t菕ng)鐨勫鐝�(xi脿n)锛屼緥濡傞亱鍕曟帶鍒躲�佹鍣ㄤ汉鎶�琛�銆�
銆�銆�5. 閱�(y墨)鐧傛垚鍍忥細鍦ㄨ秴鑱叉尝銆丆T 鎺冩弿鍎�绛夐啱(y墨)鐧傝ō鍌欎腑鐢ㄤ綔鏁�(sh霉)鎿�(j霉)铏曠悊鏍稿績銆�
銆�銆�6. 杌嶄簨鑸囪埅澶╋細婊胯冻楂樺彲闈犳�ц姹傜殑浠诲嫏闂滈嵉鍨嬬郴绲�(t菕ng)瑷▓銆�
銆�銆�7. 娓│鑸囨脯閲忥細鐐哄京闆滄脯瑭﹀剙鍣ㄦ彁渚涢潏娲荤殑淇¤櫉铏曠悊鑳藉姏銆�
EP2SGX125KF1508C4N
銆�銆�EP2SGX125KF1508C4G
銆�銆�EP2SGX125GF1508C4N
