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鐢�(ch菐n)鍝佸瀷铏�	EP2S90F780C4N
鎻忚堪	闆嗘垚闆昏矾FPGA 534 I/O 780FBGA
鍒嗛	闆嗘垚闆昏矾(IC)锛屽祵鍏ュ紡-FPGA(鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄ｅ垪)
鍒堕€犲晢	鑻辩壒鐖�
绯诲垪	Stratix?II
鎵撳寘	鎵樼洡
闆朵欢鐙€鎱�(t脿i)	娲绘€�
闆诲-闆绘簮	1.15V?1.25V
宸ヤ綔婧害	0掳C?85掳C(TJ)
鍖呰/绠�	780-BBGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏寘瑁�	780-FBGA(29x29)
鍩烘湰闆朵欢铏�	EP2S90

鐢�(ch菐n)鍝佸湒鐗�

EP2S90F780C4N

瑕�(gu墨)鏍煎弮鏁�(sh霉)

鍙法绋嬮倧杓鍨�	鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄ｅ垪
绗﹀悎REACH	鏄�
绗﹀悎姝愮洘RoHS	鏄�
鐙€鎱�(t脿i)	杞�(zhu菐n)鍏�
鏈€澶ф檪閻橀牷	717.0鍏嗚但
CLB-Max鐨勭祫鍚堝欢閬�	5.117 ns
JESD-30浠ｇ⒓	S-PBGA-B780
JESD-609浠ｇ⒓	1铏�
绺絉AM浣�	4520488
CLB鏁�(sh霉)閲�	4548.0
杓稿叆鏁�(sh霉)閲�	534.0
閭忚集鍠厓鏁�(sh霉)	90960.0
杓稿嚭鏁�(sh霉)閲�	526.0
绔瓙鏁�(sh霉)	780
鏈€浣庡伐浣滄韩搴�	0鈩�
鏈€楂樺伐浣滄韩搴�	85鈩�
绲勭箶	4548 CLBS
宄板€煎洖娴佹韩搴�(鈩�)	245
闆绘簮	1.2,1.5 / 3.3,3.3
璩囨牸鐙€鎱�(t脿i)	涓嶅悎鏍�
搴ч珮	3.5姣背
瀛愰鍒�	鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄ｅ垪
闆绘簮闆诲妯�(bi膩o)绋�	1.2浼�
鏈€灏忎緵闆婚浕澹�	1.15浼�
鏈€澶ч浕婧愰浕澹�	1.25浼�
瀹夎椤炲瀷	琛ㄩ潰璨艰
鎶€琛�(sh霉)	CMOS
婧害绛夌礆	鍏朵粬
绲傜瀹屾垚	閷妧閵�
绲傜琛ㄦ牸	鐞�
绔瓙闁撹窛	1.0姣背
绲傜浣嶇疆	搴曢儴
鏅傞枔@宄板€煎洖娴佹韩搴︽渶澶у€�(绉�)	40
闀峰害	29.0姣背
瀵害	29.0姣背
鍖呰涓婚珨鏉愭枡	濉戞枡/鐠�(hu谩n)姘фü鑴�
鍖呰浠ｇ⒓	BGA
鍖呰绛夋晥浠ｇ⒓	BGA780,28X28,40
鍖呰褰㈢媭	寤ｅ牬
鍖呰褰㈠紡	缍�(w菐ng)鏍奸櫍鍒�
鍒堕€犲晢鍖呰瑾槑	29 X 29 MM锛�1 MM闁撹窛锛岀劇閴涳紝F(xi脿n)BGA-780

鐠�(hu谩n)澧冭垏鍑哄彛鍒嗛

鐒￠墰鐙€鎱�(t脿i)/RoHS鐙€鎱�(t脿i)	鐒￠墰/绗﹀悎RoHS
姘村垎鏁忔劅鎬ф按骞�(MSL)	3(168灏忔檪)

鐗归粸

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澶氶仈(d谩)9,383,040 RAM浣�(1,172,880瀛楃瘈(ji茅))鍙敤锛岃€屼笉娓涘皯閭忚集璩囨簮
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