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鎮ㄥソ锛屾杩庝締鍒扮董搴�(k霉)闆诲瓙甯傚牬(ch菐ng)缍�(w菐ng) 鐧婚寗 | 鍏嶈不(f猫i)娉ㄥ唺(c猫)

鎮ㄦ墍鍦ㄧ殑浣嶇疆锛�闆诲瓙鍏冨櫒浠堕噰璩�(g貌u)缍�(w菐ng) > IC鐧剧 > EP2S180F1508C4N

EP2S180F1508C4N 鐧�(f膩)甯冩檪(sh铆)闁� 鏅�(sh铆)闁擄細2023/8/1 11:16:35 鏌ョ湅 闁辫畝锛�256

鐢�(ch菐n)鍝佹杩�

鐢�(ch菐n)鍝佸瀷铏�(h脿o)

EP2S180F1508C4N

鎻忚堪

闆嗘垚闆昏矾FPGA 1170 I/O 1508FBGA

鍒嗛

闆嗘垚闆昏矾(IC)锛屽祵鍏ュ紡-FPGA(鐝�(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸闄ｅ垪)

鍒堕�犲晢

鑻辩壒鐖�

绯诲垪

Stratix?II

鎵撳寘

鎵樼洡

闆朵欢鐙�鎱�(t脿i)

娲绘��

闆诲-闆绘簮

1.15V?1.25V

宸ヤ綔婧害

0掳C?85掳C(TJ)

鍖呰/绠�

1508-BBGA锛孎(xi脿n)CBGA

渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏寘瑁�

1508-FBGA(30x30)

鍩烘湰闆朵欢铏�(h脿o)

EP2S180

鐢�(ch菐n)鍝佸湒鐗�

EP2S180F1508C4N

EP2S180F1508C4N

瑕�(gu墨)鏍煎弮鏁�(sh霉)

鍙法绋嬮倧杓鍨�

鐝�(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸闄ｅ垪

绗﹀悎REACH

鏄�

绗﹀悎姝愮洘RoHS

鏄�

鐙�鎱�(t脿i)

杞�(zhu菐n)绉�

鏈�澶ф檪(sh铆)閻橀牷鐜�

717.0鍏嗚但

CLB-Max鐨勭祫鍚堝欢閬�

5.117 ns

JESD-30浠ｇ⒓

S-PBGA-B1508

JESD-609浠ｇ⒓

1铏�(h脿o)

绺絉AM浣�

9383040

CLB鏁�(sh霉)閲�

71760.0

杓稿叆鏁�(sh霉)閲�

1170.0

閭忚集鍠厓鏁�(sh霉)

179400.0

杓稿嚭鏁�(sh霉)閲�

1162.0

绔瓙鏁�(sh霉)

1508

鏈�浣庡伐浣滄韩搴�

0鈩�

鏈�楂樺伐浣滄韩搴�

85鈩�

绲勭箶

71760 CLBS

宄板�煎洖娴佹韩搴�(鈩�)

245

闆绘簮

1.2,1.5 / 3.3,3.3

璩囨牸鐙�鎱�(t脿i)

涓嶅悎鏍�

搴ч珮

3.5姣背

瀛愰鍒�

鐝�(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸闄ｅ垪

闆绘簮闆诲妯�(bi膩o)绋�

1.2浼�

鏈�灏忎緵闆婚浕澹�

1.15浼�

鏈�澶ч浕婧愰浕澹�

1.25浼�

瀹夎椤炲瀷

琛ㄩ潰璨艰

鎶�琛�(sh霉)

CMOS

婧害绛夌礆(j铆)

鍏朵粬

绲傜瀹屾垚

閷妧閵�

绲傜琛ㄦ牸

鐞�

绔瓙闁撹窛

1.0姣背

绲傜浣嶇疆

搴曢儴

鏅�(sh铆)闁揁宄板�煎洖娴佹韩搴︽渶澶у��(绉�)

30

闀�(zh菐ng)搴�

40.0姣背

瀵害

40.0姣背

鍖呰涓婚珨鏉愭枡

濉戞枡/鐠�(hu谩n)姘фü鑴�

鍖呰浠ｇ⒓

BGA

鍖呰绛夋晥浠ｇ⒓

BGA1508,39X39,40

鍖呰褰㈢媭

寤ｅ牬(ch菐ng)

鍖呰褰㈠紡

缍�(w菐ng)鏍奸櫍鍒�

鍒堕�犲晢鍖呰瑾槑

40 X 40 MM锛�1 MM闁撹窛锛孎(xi脿n)BGA-1508

鐠�(hu谩n)澧冭垏鍑哄彛鍒嗛

鐒￠墰鐙�鎱�(t脿i)/RoHS鐙�鎱�(t脿i)

鐒￠墰/绗﹀悎RoHS

姘村垎鏁忔劅鎬ф按骞�(MSL)

3(168灏忔檪(sh铆))

鐗归粸(di菐n)

  • 姣忓��(g猫)瑷�(sh猫)鍌欏閬�(d谩)12鍊�(g猫)PLL(鍥涘��(g猫)澧炲挤(qi谩ng)鍨婸LL鍜屽叓鍊�(g猫)蹇�烶LL)鍙彁渚涙摯(ku貌)闋�锛屽彲绶ㄧ▼甯跺锛屾檪(sh铆)閻樺垏鎻�锛屽(sh铆)鏅�(sh铆)PLL 閲嶉厤缃互鍙婇珮绱�(j铆)涔樻硶鍜岀浉绉�

  • 鏂板瀷鍓�(chu脿ng)鏂扮殑鑷仼鎳�(y墨ng)閭忚集妯″(ALM)鏄疭tratix II鏋舵(g貌u)鐨勫熀鏈(g貌u)寤哄锛屽彲鏈�澶ч檺搴﹀湴鎻愰珮鎬ц兘鍜岃硣婧愪娇鐢ㄦ晥鐜�

  • 澶氶仈(d谩)9,383,040 RAM浣�(1,172,880瀛楃瘈(ji茅))鍙敤锛岃�屼笉娓涘皯閭忚集璩囨簮

  • TriMatrixmemory鐢变笁鍊�(g猫)RAM濉婂ぇ灏忕祫鎴愶紝浠ュ(sh铆)鐝�(xi脿n)鐪熸鐨勯洐绔彛瀛樺劜(ch菙)鍣ㄥ拰鍏堥��(j矛n)鍏堝嚭(FIFO)绶╂矕鍗�(q奴)

  • 楂橀�烡SP妯″鎻愪緵涔樻硶鍣�(鏈�楂�450 MHz)锛屼箻娉曠疮鍔犲姛鑳藉拰鏈夐檺鑴堟矕闊挎噳(y墨ng)(FIR)婵炬尝鍣ㄧ殑灏堢敤瀵�(sh铆)鐝�(xi脿n)銆�

  • 鏅�(sh铆)閻樻帶鍒跺鏀寔鍕�(d貌ng)鎱�(t脿i)鏅�(sh铆)閻樼恫(w菐ng)绲�(lu貌)鍟熺敤/绂佺敤锛岄�欏厑瑷辨檪(sh铆)閻樼恫(w菐ng)绲�(lu貌)鎺夐浕浠ユ笡灏戠敤鎴舵ā寮忎笅鐨勫姛鑰�

  • 鏀寔楂橀�熺恫(w菐ng)绲�(lu貌)鍜岄�氫俊绺界窔妯�(bi膩o)婧�(zh菙n)锛屽寘鎷苟琛孯apidIO锛孲PI-4 2鏈�(POS-PHY 4绱�(j铆))锛孒yperTransport?鎶�琛�(sh霉)鍜孲FI-4

  • 鏀寔楂橀�熷閮ㄥ瓨鍎�(ch菙)鍣�锛屽寘鎷珼DR鍜孌DR2 SDRAM锛孯LDRAM II锛孮DR II SRAM鍜孲DR SDRAM

  • 鏀寔AlteraMegaCore? 鍔熻兘鍜孉ltera Megafunction Partners Program(AMPPSM)瀹忓姛鑳戒腑鐨勫鍊�(g猫)鐭ヨ瓨(sh铆)鐢�(ch菐n)娆�(qu谩n)瀹忓姛鑳�

  • 澶氶仈(d谩)16鍊�(g猫)鍏ㄥ眬鏅�(sh铆)閻�锛屾瘡鍊�(g猫)瑷�(sh猫)鍌欏崁(q奴)鍩熷叿鏈�24鍊�(g猫)鏅�(sh铆)閻樿硣婧�

  • 鍏锋湁DPA闆昏矾鐨勯珮閫熷樊鍒咺 / O鏀寔锛屽彲瀵�(sh铆)鐝�(xi脿n)1-Gbps鐨勬�ц兘

  • 鏀寔澶氱ó鍠鍜屽樊鍒咺 / O妯�(bi膩o)婧�(zh菙n)

  • 浣跨敤閰嶇疆姣旂壒娴佸姞瀵嗘敮鎸佽ō(sh猫)瑷�(j矛)瀹夊叏

  • 15,600鑷�179,400绛夋晥LE

  • 鏀寔閬�(yu菐n)绋嬮厤缃洿鏂�

CAD妯″瀷

EP2S180F1508C4N绗﹁櫉(h脿o)

EP2S180F1508C4N绗﹁櫉(h脿o)

EP2S180F1508C4N鑵冲嵃

EP2S180F1508C4N鑵冲嵃

ep2s180f1508c4n鎺ㄨ枽渚涙噳(y墨ng)鍟� 鏇村>

  • 鐢�(ch菐n)鍝佸瀷铏�(h脿o)
  • 渚涙噳(y墨ng)鍟�
  • 鏁�(sh霉)閲�
  • 寤犲晢
  • 灏佽/鎵硅櫉(h脿o)
  • 瑭㈠児(ji脿)

ep2s180f1508c4n璩囨枡 鏇村>

  • 鍨嬭櫉(h脿o)
  • 鎻忚堪
  • 鍝佺墝
  • 闁辫涓嬭級

ep2s180f1508c4n鍦栫墖

ep2s180f1508c4n

ep2s180f1508c4n鐢�(ch菐n)鍝�

ep2s180f1508c4n鍙冩暩(sh霉)

  • 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″Three Reasons to Use FPGA's in Industrial Designs
  • 妯�(bi膩o)婧�(zh菙n)鍖呰7
  • 椤炲垾闆嗘垚闆昏矾 (IC)
  • 瀹跺涵宓屽叆寮� - FPGA锛堢従(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸闄ｅ垪锛�
  • 绯诲垪Stratix® II
  • LAB/CLB鏁�(sh霉)8970
  • 閭忚集鍏冧欢/鍠厓鏁�(sh霉)179400
  • RAM 浣嶇附瑷�(j矛)9383040
  • 杓稿叆/杓稿嚭鏁�(sh霉)1170
  • 闁�鏁�(sh霉)-
  • 闆绘簮闆诲1.15 V ~ 1.25 V
  • 瀹夎椤炲瀷琛ㄩ潰璨艰
  • 宸ヤ綔婧害0°C ~ 85°C
  • 灏佽/澶栨1508-BBGA
  • 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�1508-FBGA锛�30x30锛�
  • 閰嶇敤544-1701-ND - DSP PRO KIT W/SII EP2S180N
  • 鍏跺畠鍚嶇ū544-1887EP2S180F1508C4N-ND