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鍙冩暩(sh霉)

鍨嬭櫉锛欵P2AGX65DF25C5G
銆€銆€鍝佺墝锛欰ltera (Intel FPGA)
銆€銆€绯诲垪锛欳yclone II
銆€銆€閭忚集鍠厓鏁�(sh霉)閲忥細绱� 65K LE (Logic Elements)
銆€銆€宓屽叆寮忓瓨鍎插櫒锛氶珮閬�(d谩) 1.4 Mb
銆€銆€DSP 妯″锛氱劇
銆€銆€I/O 寮曡叧鏁�(sh霉)锛�308
銆€銆€宸ヤ綔闆诲锛�1.2V 鏍稿績闆诲 / 3.3V I/O 闆诲
銆€銆€灏佽椤炲瀷锛欶BGA (Fine Pitch Ball Grid Array)
銆€銆€灏佽灏哄锛�25x25 mm
銆€銆€宸ヤ綔婧害鑼冨湇锛�-40掳C 鑷� +85掳C
銆€銆€鏈€灏忓伐浣滈牷鐜囷細0 MHz
銆€銆€鏈€澶у伐浣滈牷鐜囷細312 MHz

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EP2AGX65DF25C5G 鐨勪富瑕佺壒鎬у寘鎷細
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EP2AGX65DF25C5G 鑺墖寤ｆ硾鎳�(y墨ng)鐢ㄤ簬浠ヤ笅闋�(l菒ng)鍩燂細
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