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EP2AGX45DF25C4N 鏄竴娆剧敱 Altera锛堢従(xi脿n)鐐� Intel FPGA 閮ㄩ杸锛夌敓鐢�(ch菐n)鐨� Stratix II 绯诲垪鐨� FPGA 鑺墖銆傝┎绯诲垪鑺墖涓昏鐢ㄤ簬楂樻€ц兘瑷堢畻銆侀€氫俊鍩虹(ch菙)瑷�(sh猫)鏂�銆佷俊铏熻檿鐞嗗拰鍏朵粬寰�(f霉)闆滈倧杓ō(sh猫)瑷堟噳(y墨ng)鐢�銆傞€欐 FPGA 鎻愪緵浜嗚睈瀵岀殑鏁�(sh霉)瀛椾俊铏熻檿鐞� (DSP) 鍔熻兘鍜岄珮閫熸敹鐧�(f膩)鍣紝鑳藉婊胯冻澶氱ó寰�(f霉)闆滅郴绲�(t菕ng)鐨勯渶姹�銆�
銆€銆€Stratix II 绯诲垪閲囩敤浜� 90nm 鍒剁▼宸ヨ棟锛屾彁渚涗簡楂樺瘑搴﹂倧杓柈鍏冨拰闈堟椿鐨勬灦妲�(g貌u)锛屼娇寰楃敤鎴惰兘澶犲湪鍠€嬪櫒浠朵腑瀵︾従(xi脿n)寰�(f霉)闆滅殑鏁�(sh霉)瀛椾俊铏熻檿鐞嗙畻娉曞拰鍗�(xi茅)璀拌綁(zhu菐n)鎻涚瓑鍔熻兘銆�

鍙冩暩(sh霉)

鍨嬭櫉锛欵P2AGX45DF25C4N
銆€銆€绯诲垪锛歋tratix II
銆€銆€鍒剁▼宸ヨ棟锛�90nm
銆€銆€閭忚集鍠厓鏁�(sh霉)锛氱磩 45,000
銆€銆€RAM锛�1,620 Kb
銆€銆€DSP 妯″鏁�(sh霉)閲忥細360
銆€銆€I/O 寮曡叧鏁�(sh霉)锛�870
銆€銆€閰嶇疆鏂瑰紡锛氫富鍕曚覆琛� (AS), 琚嫊涓茶 (PS), JTAG
銆€銆€宸ヤ綔婧害鑼冨湇锛�-40掳C 鑷� +85掳C
銆€銆€灏佽椤炲瀷锛欶BGA

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EP2AGX45DF25C4N 鍏峰倷浠ヤ笅闂�(gu膩n)閸电壒鎬э細
銆€銆€1. 楂樻€ц兘锛氶噰鐢� 90nm 鎶€琛�(sh霉)绡€(ji茅)榛炲埗閫�锛屽叿鏈夊挤澶х殑閭忚集璩囨簮鍜� DSP 铏曠悊鑳藉姏銆�
銆€銆€2. 闆嗘垚搴﹂珮锛氭彁渚涘閬� 45,000 鍊嬮倧杓柈鍏冧互鍙� 360 鍊� DSP 妯″锛岄仼鍚堝京(f霉)闆滅畻娉曞鐝�(xi脿n)銆�
銆€銆€3. 鏀寔楂橀€熸帴鍙ｏ細鍏�(n猫i)缃珮閫熸敹鐧�(f膩)鍣�锛屽彲鏀寔楂橀仈 6.375Gbps 鐨勬暩(sh霉)鎿�(j霉)鍌宠几閫熺巼銆�
銆€銆€4. 澶氱ó瀛樺劜閬搁爡锛氬寘鍚祵鍏ュ紡 RAM 濉婏紝绺�?c猫)钀樼箾?1,620 Kb锛岀敤浜庣珐瀛樺拰绶╂矕鍔熻兘銆�
銆€銆€5. 闈堟椿鎬у挤锛氭敮鎸佸绋厤缃ā寮忥紙濡� AS銆丳S 鍜� JTAG锛�锛屼究浜庨枊鐧�(f膩)鑸囪(di脿o)瑭�銆�
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