鏅傞枔锛�2023/7/28 11:59:57
闁辫畝锛�812
鐢�(ch菐n)鍝佸瀷铏� | EP1SGX10DF672C5N |
鎻忚堪 | 闆嗘垚闆昏矾FPGA 362 I / O 672FBGA |
鍒嗛 | 闆嗘垚闆昏矾(IC)锛屽祵鍏ュ紡-FPGA(鐝�(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪) |
鍒堕�犲晢 | 鑻辩壒鐖� |
绯诲垪 | Stratix?GX |
鎵撳寘 | 鎵樼洡 |
闆朵欢鐙�鎱�(t脿i) | 閬庢檪鐨� |
闆诲-闆绘簮 | 1.425V?1.575V |
宸ヤ綔婧害 | 0掳C?85掳C(TJ) |
鍖呰/绠� | 672-BBGA锛孎(xi脿n)CBGA |
渚涙噳鍟嗚ō鍌欏寘瑁� | 672-FBGA(27x27) |
鍩烘湰闆朵欢铏� | EP1SGX10 |
EP1SGX10DF672C5N
鍙法绋嬮倧杓鍨� | 鐝�(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪 |
绗﹀悎姝愮洘RoHS | 鏄� |
鐙�鎱�(t脿i) | 杞夊叆 |
JESD-30浠ｇ⒓ | S-PBGA-B672 |
JESD-609浠ｇ⒓ | 1铏� |
绺絉AM浣� | 920448 |
CLB鏁�(sh霉)閲� | 1200.0 |
杓稿叆鏁�(sh霉)閲� | 362.0 |
閭忚集鍠厓鏁�(sh霉) | 10570.0 |
杓稿嚭鏁�(sh霉)閲� | 362.0 |
绔瓙鏁�(sh霉) | 672 |
鏈�浣庡伐浣滄韩搴� | 0鈩� |
鏈�楂樺伐浣滄韩搴� | 85鈩� |
绲勭箶 | 1200 CLBS |
宄板�煎洖娴佹韩搴�(鈩�) | 245 |
闆绘簮 | 1.5,1.5 / 3.3 |
璩囨牸鐙�鎱�(t脿i) | 涓嶅悎鏍� |
搴ч珮 | 3.5姣背 |
瀛愰鍒� | 鐝�(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪 |
闆绘簮闆诲妯欑ū | 1.5浼� |
鏈�灏忎緵闆婚浕澹� | 1.425浼� |
鏈�澶ч浕婧愰浕澹� | 1.575浼� |
瀹夎椤炲瀷 | 琛ㄩ潰璨艰 |
鎶�琛� | CMOS |
婧害绛夌礆 | 鍏朵粬 |
绲傜瀹屾垚 | 閷�/閵�/閵�(Sn / Ag / Cu) |
绲傜琛ㄦ牸 | 鐞� |
绔瓙闁撹窛 | 1.0姣背 |
绲傜浣嶇疆 | 搴曢儴 |
鏅傞枔@宄板�煎洖娴佹韩搴︽渶澶у��(绉�) | 40 |
闀峰害 | 27.0姣背 |
瀵害 | 27.0姣背 |
鍖呰涓婚珨鏉愭枡 | 濉戞枡/鐠�(hu谩n)姘фü鑴� |
鍖呰浠ｇ⒓ | BGA |
鍖呰绛夋晥浠ｇ⒓ | BGA672,26X26,40 |
鍖呰褰㈢媭 | 寤ｅ牬 |
鍖呰褰㈠紡 | 缍�(w菐ng)鏍奸櫍鍒� |
鍒堕�犲晢鍖呰瑾槑 | 27 X 27 MM锛�1 MM闁撹窛锛孎(xi脿n)BGA-672 |
鐒￠墰鐙�鎱�(t脿i) | 鐒￠墰 |
姘村垎鏁忔劅鎬ф按骞�(MSL) | 3(168灏忔檪) |
鈻犳敹鐧�(f膩)鍣ㄦā濉婂姛鑳藉涓嬶細
鈼忓付CDR鐨勯珮閫熶覆琛屾敹鐧�(f膩)鍣ㄩ�氶亾鍙彁渚涙瘡绉�500鍏嗕綅(Mbps)鍒�3.1875 Gbps鐨勫叏闆欏伐鎿嶄綔
鈼忚ō鍌欏叿鏈�4銆�8銆�16 鎴�20鍊嬮珮閫熶覆琛屾敹鐧�(f膩)鍣ㄩ�氶亾锛屽彲鎻愪緵楂橀仈127.5 Gbps鐨勫叏闆欏伐涓茶甯跺
鈼忔敮鎸佸熀浜庢敹鐧�(f膩)鍣ㄧ殑鍗�(xi茅)璀帮紝鍖呮嫭10鍗冨厗浠ュお缍�(w菐ng)閫ｆ帴鍠厓鎺ュ彛(XAUI)锛屽崈鍏嗕互澶恫(w菐ng)(GigE)鍜孲ONET / SDH
鈼忓吋瀹筆CI Express锛孲MPTE 292M锛屽厜绾栭�氶亾鍜屼覆琛孯apidIO I / O妯欐簴
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鈼忓彲绶ㄧ▼鏀剁櫦(f膩)鍣ㄥ埌FPGA鎺ュ彛锛屾敮鎸�8浣嶏紝10浣�锛�16浣嶅拰20浣嶅鐨勬暩(sh霉)鎿�(j霉)璺緫
鈼�1.5V鍋介浕娴佹ā寮忛倧杓�(PCML)锛岄仼鐢ㄤ簬500 Mbps鑷�3.1875 Gbps
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鈼忓収(n猫i)缃嚜娓�(BIST)
鈼忕啽鎻掓嫈淇濊闆昏矾
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鈼忛�熺巼鍖归厤鍣ㄧ鍚圙igE妯″紡鐨処EEE 802.3-2002 鍜孹AUI妯″紡鐨処EEE 802-3ae
鈼忛�氶亾缍佸畾绗﹀悎IEEE 802.3ae(鍍呴仼鐢ㄤ簬XAUI妯″紡)
鈼忓鏈夊繀瑕�锛岃ō鍌欏彲浠ョ篂閬庢煇浜涙敹鐧�(f膩)鍣ㄦā濉婂姛鑳�
鈻燜PGA鍔熻兘濡備笅锛�
鈼�10570鑷�41250鍊嬮倧杓厓绱�(LE)
鈼忓閬�3,423,744鍊婻AM浣�(427,968瀛楃瘈(ji茅))鍙敤锛岃�屼笉鏈冩笡灏戦倧杓硣婧�
鈼忕敱涓夊�婻AM濉婂ぇ灏忕祫鎴愮殑TriMatrix?瀛樺劜鍣�锛岀敤浜庡鐝�(xi脿n)鐪熸鐨勯洐绔彛瀛樺劜鍣ㄥ拰鍏堥�插厛鍑�(FIFO)绶╂矕鍗�(q奴)
鈼忔渶澶�16鍊嬪叏灞�鏅傞悩缍�(w菐ng)绲★紝姣忓�嬭ō鍌欏崁(q奴)鍩熸渶澶�22鍊嬪崁(q奴)鍩熸檪閻樼恫(w菐ng)绲�
鈼忛珮閫烡SP妯″鎻愪緵涔樻硶鍣�(楂樹簬300 MHz)锛屼箻娉曠疮鍔犲姛鑳藉拰鏈夐檺鑴堟矕闊挎噳(FIR)婵炬尝鍣ㄧ殑灏堢敤瀵︾従(xi脿n)
鈼� 姣忓�嬭ō鍌欐渶澶氬叓鍊嬮�氱敤閹栫浉鐠�(hu谩n)(鍥涘�嬪寮峰瀷PLL鍜屽洓鍊嬪揩閫烶LL)鍙彁渚涢牷璀滄摯灞�锛屽彲绶ㄧ▼甯跺锛屾檪閻樺垏鎻�锛屽鏅侾LL 閲嶉厤缃互鍙婇珮绱氫箻娉曞拰鐩镐綅杞夌Щ
鈼忔敮鎸佸绋柈绔拰宸垎I / O 妯欐簴
鈼忓閬�45鍊嬮�氶亾涓婄殑楂橀�熸簮鍚屾宸垎I / O鏀寔锛屽彲瀵︾従(xi脿n)1 Gbps鎬ц兘
鈼忔敮鎸佹簮鍚屾绺界窔妯欐簴锛屽寘鎷�10 Gb浠ュお缍�(w菐ng)XSBI锛屽苟琛孯apidIO锛孶TOPIA IV锛岀恫(w菐ng)绲″垎绲勬祦鎺ュ彛(NPSI)锛孒yperTransportTM 鎶�琛擄紝SPI-4绗簩闅庢(POS-PHY 4绱�)鍜孲FI-4
鈼忔敮鎸侀珮閫熷閮ㄥ瓨鍎插櫒锛屽寘鎷浂绺界窔鍛ㄨ綁(ZBT)SRAM锛屽洓鏁�(sh霉)鎿�(j霉)閫熺巼(QDR鍜孮DRII)SRAM锛岄洐鏁�(sh霉)鎿�(j霉)閫熺巼(DDR)SDRAM锛孌DR蹇�熷懆鏈烺AM (FCRAM)鍜屽柈鏁�(sh霉)鎿�(j霉)閫熺巼(SDR) )SDRAM
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鈼廘VDS鎺ユ敹鍣ㄩ�氶亾涓婄殑鍕曟厠(t脿i)鐩镐綅灏嶆簴
