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椤炲瀷锛氭檪閻樼珐娌栧櫒
銆€銆€杓稿叆鏍煎紡锛歀VPECL, LVDS, CMOS
銆€銆€杓稿嚭鏁�(sh霉)閲忥細8璺�
銆€銆€宸ヤ綔闆诲鑼冨湇锛�3.0V 鑷� 3.6V
銆€銆€鏈€澶ц几鍑洪牷鐜囷細156.25MHz
銆€銆€鐩镐綅鎶栧嫊锛氬皬浜�1ps RMS
銆€銆€闆绘簮闆绘祦锛�40mA 鍏稿瀷鍊�
銆€銆€灏佽褰㈠紡锛�32 寮曡叧 LLP 灏佽 (4mm 脳 4mm)

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