鏅傞枔锛�2023/7/21 19:58:59
闁辫畝锛�429
鐢�(ch菐n)鍝佸瀷铏� | CC1350F128RGZR |
鎻忚堪 | 闆嗘垚闆昏矾RF TXRX + MCU BLUETOOTH 48VQFN |
鍒嗛 | RF / IF鍜孯FID锛屽皠闋绘敹鐧�(f膩)鍣↖C |
鍒堕�犲晢 | 寰峰窞鍎�鍣� |
绯诲垪 | SimpleLink? |
鎵撳寘 | 鍒囧壊甯�(CT) |
闆朵欢鐙�鎱�(t脿i) | 娲绘�� |
闆诲-闆绘簮 | 1.8V?3.8V |
宸ヤ綔婧害 | -40掳C?85掳C |
鍖呰/绠� | 48-VFQFN瑁搁湶鐒婄洡 |
渚涙噳鍟嗚ō鍌欏寘瑁� | 48 VQFN(7x7) |
鍩烘湰闆朵欢铏� | CC1350 |
CC1350F128RGZR
鍒堕�犲晢鍖呰瑾槑 | VQFN-48 |
绗﹀悎REACH | 鏄� |
绗﹀悎姝愮洘RoHS | 鏄� |
绗﹀悎涓湅RoHS | 鏄� |
鐙�鎱�(t脿i) | 娲绘�� |
椤炲瀷 | TxRx + MCU |
灏勯牷绯诲垪/妯欐簴 | 钘嶇墮 |
鍗�(xi茅)璀� | 钘嶇墮v4.2 |
ADC閫氶亾 | 鏄� |
鍦板潃绺界窔瀵害 | 0.0 |
浣嶅ぇ灏� | 32 |
DMA閫氶亾 | 鏄� |
澶栭儴鏁�(sh霉)鎿�(j霉)绺界窔瀵害 | 0.0 |
JESD-30浠ｇ⒓ | S-PQCC-N48 |
JESD-609浠ｇ⒓ | e4 |
I / O绶氭暩(sh霉) | 30.0 |
绔瓙鏁�(sh霉) | 48 |
鐗囦笂绋嬪簭ROM瀵害 | 8.0 |
鏈�浣庡伐浣滄韩搴� | -40鈩� |
鏈�楂樺伐浣滄韩搴� | 85鈩� |
鍖呰涓婚珨鏉愭枡 | 濉戞枡/鐠�(hu谩n)姘фü鑴� |
鍖呰浠ｇ⒓ | HVQCCN |
鍖呰褰㈢媭 | 鍥涙柟褰� |
鍖呰褰㈠紡 | 鑺墖杓夐珨锛屾暎鐔辩墖/濉炲瓙锛岃吉寤撴サ钖� |
宄板�煎洖娴佹韩搴�(鈩�) | 260 |
PWM閫氶亾 | 鏄� |
RAM(瀛楃瘈(ji茅)) | 20480.0 |
ROM鍙法绋嬫�� | 闁� |
ROM(瀛�) | 131072 |
搴ч珮 | 1.0姣背 |
閫熷害 | 48.0鍏嗚但 |
闆绘簮闆诲妯欑ū | 3.0浼� |
鏈�灏忎緵闆婚浕澹� | 1.8浼� |
鏈�澶ч浕婧愰浕澹� | 3.8浼� |
瀹夎椤炲瀷 | 琛ㄩ潰璨艰 |
鎶�琛� | CMOS |
婧害绛夌礆 | 鐢�(ch菐n)妤�(y猫) |
绲傜瀹屾垚 | 閹�/閳�/閲�(Ni / Pd / Au) |
绲傜琛ㄦ牸 | 鐒￠墰 |
绔瓙闁撹窛 | 0.5姣背 |
绲傜浣嶇疆 | QUAD |
鏅傞枔@宄板�煎洖娴佹韩搴︽渶澶у��(绉�) | 鏈鏄� |
闀峰害 | 7.0姣背 |
瀵害 | 7.0姣背 |
闄勫姞鍔熻兘 | 渚�32.768KHZ妯欑ū鏅堕珨鏅傞悩 |
RoHS鐙�鎱�(t脿i) | 绗﹀悎ROHS3 |
姘村垎鏁忔劅鎬ф按骞�(MSL) | 3(168灏忔檪) |
鈼忎笘鐣屼笂绗竴鍊嬮洐闋�(浣庝簬1 GHz鍜�2.4 GHz)鐒＄窔寰帶鍒跺櫒
鈼忓井鎺у埗鍣�
銆傚挤澶х殑ARM?Cortex?-M3
銆侲EMBCCoreMark?寰楀垎锛�142
銆侲EMBC ULPBench?寰楀垎锛�158
銆傛檪閻橀�熷害楂橀仈48MHz
銆�128KB鐨勭郴绲�(t菕ng)鍏у彲绶ㄧ▼闁冨瓨
銆�8KB SRAM鐢ㄤ簬楂橀�熺珐瀛�(鎴栦綔鐐洪�氱敤RAM)
銆�20KB瓒呬綆娉勬紡SRAM
銆�2寮曡叧cJTAG鍜孞TAG瑾胯│
銆傛敮鎸佺┖涓�(OTA)鏇存柊
鈼忚秴浣庡姛鑰楀偝鎰熷櫒鎺у埗鍣�
銆傚彲浠ュ緸绯荤当(t菕ng)鍏朵綑閮ㄥ垎鑷富閬嬭
銆�16浣嶆灦妲�
銆�2KB鐢ㄤ簬浠ｇ⒓鍜屾暩(sh霉)鎿�(j霉)鐨勮秴浣庢硠婕廠RAM
鈼忛珮鏁堢殑浠ｇ⒓澶у皬鏋舵锛屽皣TI-RTOS鐨勫悇鍊嬮儴鍒�锛岄﹨鍕曠▼搴�锛孊luetooth?浣庤兘鑰楁帶鍒跺櫒鍜孊ootloader鏀惧湪ROM涓�
鈼忕鍚圧oHS鐨勫皝瑁�
銆�7姣背脳7姣背RGZ VQFN48(30鍊婫PIO)
鈼忓懆閭婅ō鍌�
銆傛墍鏈夋暩(sh霉)瀛楀瑷紩鑵抽兘鍙互璺敱鑷充换浣旼PIO
銆傚洓鍊嬮�氱敤瀹氭檪鍣ㄦā濉�(鍏��16浣嶆垨鍥涘��32浣嶅畾鏅傚櫒锛屾瘡鍊婸WM)
銆�12浣岮DC锛�200 ksamples / s锛�8閫氶亾妯℃摤MUX
銆傞�ｇ簩(x霉)鏅傞枔姣旇純鍣�
銆傝秴浣庡姛鑰楁檪閻樻瘮杓冨櫒
?锛熷垹骞婂眽濞忛珶?/p>
銆備覆鍙�
銆�2鍊婼SI(SPI锛孧ICROWIRE锛孴I)
銆侷2C锛孖2S
銆傚鏅傛檪閻�(RTC)
銆侫ES-128瀹夊叏妯″
銆傜湡闅ㄦ鏁�(sh霉)鐧�(f膩)鐢熷櫒(TRNG)
銆傛敮鎸佸叓鍊嬮浕瀹瑰紡鎰熸噳鎸夐垥
銆傞泦鎴愭韩搴﹀偝鎰熷櫒
鈼忓閮ㄧ郴绲�(t菕ng)
銆傜墖涓婂収閮―C-DC杞夋彌鍣�
銆傝垏SimpleLink?CC1190鍜孋C2592鑼冨湇鎿村睍鍣ㄧ殑鐒＄斧闆嗘垚
鈼忎綆闆婚噺
銆傚闆绘簮闆诲鑼冨湇锛�1.8鑷�3.8 V
銆傛帴鏀讹細5.4 mA(Sub-1 GHz)锛�6.4 mA(钘嶇墮浣庡姛鑰楋紝2.4 GHz)
銆傚湪+10 dBm鏅傜櫦(f膩)灏勶細13.4 mA(Sub-1 GHz)
銆備互+9 dBm鐧�(f膩)灏勶細22.3 mA(钘嶇墮浣庡姛鑰楋紝2.4 GHz)
銆傚湪+0 dBm鏅傜櫦(f膩)灏勶細10.5 mA(钘嶇墮浣庡姛鑰�锛�2.4 GHz)
銆傛湁婧愭ā寮廙CU 48 MHz閬嬭Coremark锛�2.5 mA(51 渭A / MHz)
銆備富鍕曟ā寮廙CU锛�48.5 CoreMark / mA
銆�24 MHz鏅傜殑鏈夋簮妯″紡鍌虫劅鍣ㄦ帶鍒跺櫒锛�0.4 mA + 8.2 渭A / MHz
銆傚偝鎰熷櫒鎺у埗鍣紝姣忕鍩�(zh铆)琛屼竴娆″枤閱�锛屽煼(zh铆)琛屼竴娆�12浣岮DC閲囨ǎ锛�0.95 渭A
銆傚緟姗燂細0.7 渭A(RTC閬嬭浠ュ強RAM鍜孋PU淇濈暀)
銆傞棞鏂凤細185 nA(澶栭儴浜嬩欢鍠氶啋)
CC1350F128RGZR绗﹁櫉
CC1350F128RGZR鑵冲嵃
