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鍏�(n猫i)鏍革細ARM Cortex-M4 with FPU
銆€銆€涓婚牷锛氭渶楂�120MHz
銆€銆€闁冨瓨锛�512KB
銆€銆€SRAM锛�192KB
銆€銆€I/O寮曡叧锛氭渶澶�78鍊�(g猫)
銆€銆€ADC閫氶亾锛�12浣嶇簿搴�锛屾渶澶�20鍊�(g猫)杓稿叆閫氶亾
銆€銆€DAC閫氶亾锛�10浣嶇簿搴�锛屾渶澶�2鍊�(g猫)杓稿嚭閫氶亾
銆€銆€閫氫俊鎺ュ彛锛歋PI銆両2C銆乁SART
銆€銆€瀹氭檪(sh铆)鍣細楂樼礆(j铆)瀹氭檪(sh铆)鍣ㄥ拰閫氱敤瀹氭檪(sh铆)鍣�
銆€銆€灏佽褰㈠紡锛歀QFP64
銆€銆€宸ヤ綔婧害锛�-40掳C 鑷� +85掳C

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