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鎮ㄥソ锛屾杩庝締(l谩i)鍒扮董搴�(k霉)闆诲瓙甯傚牬(ch菐ng)缍�(w菐ng) 鐧婚寗 | 鍏嶈不(f猫i)娉ㄥ唺(c猫)

鎮ㄦ墍鍦ㄧ殑浣嶇疆锛�闆诲瓙鍏冨櫒浠堕噰璩�(g貌u)缍�(w菐ng) > IC鐧剧 > 5SGXEA7K2F40C2N

5SGXEA7K2F40C2N 鐧�(f膩)甯冩檪(sh铆)闁� 鏅�(sh铆)闁擄細2023/8/1 11:06:45 鏌ョ湅 闁辫畝锛�242

鐢�(ch菐n)鍝佹杩�

鐢�(ch菐n)鍝佸瀷铏�(h脿o)

5SGXEA7K2F40C2N

鎻忚堪

闆嗘垚闆昏矾FPGA 696 I/O 1517FBGA

鍒嗛

闆嗘垚闆昏矾(IC)锛屽祵鍏ュ紡-FPGA(鐝�(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸(m茅n)闄ｅ垪)

鍒堕�犲晢

鑻辩壒鐖�

绯诲垪

Stratix?V GX

鎵撳寘

鎵樼洡(p谩n)

闆朵欢鐙�鎱�(t脿i)

娲绘��

闆诲-闆绘簮

0.87V?0.93V

宸ヤ綔婧害

0掳C?85掳C(TJ)

鍖呰/绠�

1517-BBGA锛孎(xi脿n)CBGA

渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏寘瑁�

1517-FBGA(40x40)

鍩烘湰闆朵欢铏�(h脿o)

5SGXEA7

鐢�(ch菐n)鍝佸湒鐗�

5SGXEA7K2F40C2N

5SGXEA7K2F40C2N

瑕�(gu墨)鏍煎弮鏁�(sh霉)

鍙法绋嬮倧杓鍨�

鐝�(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸(m茅n)闄ｅ垪

绗﹀悎REACH

鏄�

绗﹀悎姝愮洘RoHS

鏄�

鐙�鎱�(t脿i)

杞�(zhu菐n)鍏�

JESD-30浠ｇ⒓

S-PBGA-B1517

绺絉AM浣�

51200000

CLB鏁�(sh霉)閲�

23472.0

杓稿叆鏁�(sh霉)閲�

696.0

閭忚集鍠厓鏁�(sh霉)

622000.0

杓稿嚭鏁�(sh霉)閲�

696.0

绔瓙鏁�(sh霉)

1517

鏈�浣庡伐浣滄韩搴�

0鈩�

鏈�楂樺伐浣滄韩搴�

85鈩�

绲勭箶

23472 CLBS

闆绘簮

0.85,1.5,2.5,2.5 / 3,1.2 / 3

璩囨牸鐙�鎱�(t脿i)

涓嶅悎鏍�

搴ч珮

3.5姣背

瀛愰鍒�

鐝�(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸(m茅n)闄ｅ垪

闆绘簮闆诲妯�(bi膩o)绋�

0.9浼�

鏈�灏忎緵闆婚浕澹�

0.87浼�

鏈�澶ч浕婧愰浕澹�

0.93浼�

瀹夎椤炲瀷

琛ㄩ潰璨艰

鎶�琛�(sh霉)

CMOS

婧害绛夌礆(j铆)

鍏朵粬

绲傜琛ㄦ牸

鐞�

绔瓙闁撹窛

1.0姣背

绲傜浣嶇疆

搴曢儴

闀�(zh菐ng)搴�

40.0姣背

瀵害

40.0姣背

鍖呰涓婚珨鏉愭枡

濉戞枡/鐠�(hu谩n)姘фü(sh霉)鑴�

鍖呰浠ｇ⒓

BGA

鍖呰绛夋晥浠ｇ⒓

BGA1517,39X39,40

鍖呰褰㈢媭

寤ｅ牬(ch菐ng)

鍖呰褰㈠紡

缍�(w菐ng)鏍奸櫍鍒�

鍒堕�犲晢鍖呰瑾�(shu艒)鏄�

FBGA-1517

鐠�(hu谩n)澧冭垏鍑哄彛鍒嗛

鐒�(w煤)閴涚媭鎱�(t脿i)/RoHS鐙�鎱�(t脿i)

鐒�(w煤)閴�/绗﹀悎RoHS

姘村垎鏁忔劅鎬ф按骞�(MSL)

3(168灏忔檪(sh铆))

鐗归粸(di菐n)

  • 鎶�琛�(sh霉)

  • 28绱嶇背TSMC鍒剁▼鎶�琛�(sh霉)

  • 0.85V鎴�0.9V鍏�(n猫i)鏍搁浕澹�

  • 浣庡姛鑰椾覆琛屾敹鐧�(f膩)鍣�

  • Stratix V GT鍣ㄤ欢涓婄殑28.05-Gbps鏀剁櫦(f膩)鍣�

  • 鐢ㄤ簬XFP锛孲FP +锛孮SFP锛孋FP鍏夋ā濉婄殑闆诲瓙鑹叉暎瑁�(b菙)鍎�(EDC)

  • 鑷仼鎳�(y墨ng)绶氭�у拰姹虹瓥鍙嶉鍧囪　

  • 鐧�(f膩)灏勬(j墨)闋�(y霉)鍔犻噸鍜屽幓鍔犻噸

  • 鍠��(g猫)閫氶亾鐨勫嫊(d貌ng)鎱�(t脿i)閲嶆柊閰嶇疆

  • 鐗囦笂鍎�鍣�(EyeQ闈炰镜鍏ュ紡鏁�(sh霉)鎿�(j霉)鐪煎湒鐩�(ji膩n)鎺�)

  • 鑳屾澘鍔熻兘

  • 姣忕600鍏嗕綅(Mbps)鍒�12.5 Gbps鐨勬暩(sh霉)鎿�(j霉)閫熺巼鑳藉姏

  • 閫氱敤I / O(GPIO)

  • 1.6 Gbps LVDS

  • 1,066-MHz澶栭儴瀛樺劜(ch菙)鍣ㄦ帴鍙�

  • 鐗囦笂鍖归厤(OCT)

  • 鎵�鏈塖tratix V鍣ㄤ欢鐨�1.2V鑷�3.3V鎺ュ彛

  • 宓屽叆寮廐ardCopy 濉�

  • PCIe Gen3锛孏en2鍜孏en1瀹屾暣鍗�(xi茅)璀版＇锛寈1 / x2 / x4 / x8绔粸(di菐n)鍜屾牴绔彛

  • 宓屽叆寮忔敹鐧�(f膩)鍣ㄧ‖鏍窱P

  • 鍥犵壒鎷夎偗鐗╃悊绶ㄧ⒓瀛愬堡(PCS)

  • 鍗冨厗浠ュお缍�(w菐ng)(GbE)鍜孹AUI PCS

  • 10G浠ュお缍�(w菐ng)PCS

  • 涓茶RapidIO?(SRIO)PCS

  • 閫氱敤鍏叡鐒�(w煤)绶氶浕鎺ュ彛(CPRI)PCS

  • 鍗冨厗鐒�(w煤)婧愬厜缍�(w菐ng)绲�(lu貌)(GPON)PCS

  • 闆绘簮绠＄悊

  • 鍙法绋嬮浕婧愭妧琛�(sh霉)

  • Quartus II闆嗘垚鐨凱owerPlay鍔熻�楀垎鏋�

  • 楂樻�ц兘鑺竷

  • 鍏锋湁鍥涘��(g猫)瀵勫瓨鍣ㄧ殑澧炲挤(qi谩ng)鍨婣LM

  • 鏀归��(j矛n)鐨勮矾鐢辨灦妲�(g貌u)娓涘皯浜嗘搧濉炲苟绺煭浜嗙法璀檪(sh铆)闁�

  • 宓屽叆寮忓収(n猫i)瀛樺

  • M20K锛�20 Kbit锛屽付鏈夌‖閷�(cu貌)瑾ょ尘姝ｇ⒓(ECC)

  • MLAB锛�640浣�

  • 鍙畩绮惧害DSP妯″

  • 楂橀仈(d谩)600 MHz鐨勬�ц兘

  • 鏈(j墨)鏀寔淇¤櫉(h脿o)铏曠悊锛岀簿搴﹀緸9x9鍒�54x54

  • 鏂扮殑鏈(j墨)27x27涔樻硶妯″紡

  • 鐢ㄤ簬鑴堝嫊(d貌ng)鏈夐檺鑴堟矕闊挎噳(y墨ng)(FIR)鐨�64浣嶇疮鍔犲櫒鍜岀礆(j铆)鑱�(li谩n)

  • 宓屽叆寮忓収(n猫i)閮ㄧ郴鏁�(sh霉)瀛樺劜(ch菙)鍣�

  • 闋�(y霉)鍔犳硶鍣�/娓涙硶鍣ㄦ彁楂樹簡鏁堢巼

  • 杓稿嚭鏁�(sh霉)閲忕殑澧炲姞鍏佽ū鏇村鐨勭崹(d煤)绔嬩箻娉曞櫒

  • 灏忔暩(sh霉)鍒嗛牷PLL

  • 鍏锋湁涓夐殠delta-sigma瑾�(di脿o)鍒剁殑鍒�?j菒n)?sh霉)妯″紡

  • 鏁存暩(sh霉)妯″紡

  • 绮剧⒑鐨勬檪(sh铆)閻樺悎鎴�锛屾檪(sh铆)閻樺欢閬茶(b菙)鍎熷拰闆跺欢閬茬珐娌栧櫒(ZDB)

  • 鏅�(sh铆)閻樼恫(w菐ng)绲�(lu貌)

  • 800 MHz鏋舵(g貌u)鏅�(sh铆)閻�

  • 鍏ㄥ眬锛岃薄闄愬拰澶栧湇鏅�(sh铆)閻樼恫(w菐ng)绲�(lu貌)

  • 鍙互闂�(gu膩n)闁夋湭浣跨敤鐨勬檪(sh铆)閻樼恫(w菐ng)绲�(lu貌)浠ラ檷浣庡嫊(d貌ng)鎱�(t脿i)鍔熻��

  • 瑷�(sh猫)鍌欓厤缃�

  • 涓茶鍜屽苟琛岄杻瀛樻帴鍙�

  • 澧炲挤(qi谩ng)鐨勯珮绱�(j铆)鍔犲瘑妯�(bi膩o)婧�(zh菙n)(AES)瑷�(sh猫)瑷�(j矛)瀹夊叏鍔熻兘

  • 闃茬鏀�

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  • FBGA灏佽锛屽付鏈夊皝瑁濆収(n猫i)鐨勫幓鑰﹂浕瀹瑰櫒

  • 閴涘拰绗﹀悎RoHS鐨勭劇(w煤)閴涢伕闋�(xi脿ng)

  • HardCopy V閬风Щ

CAD妯″瀷

5SGXEA7K2F40C2N绗﹁櫉(h脿o)

5SGXEA7K2F40C2N绗﹁櫉(h脿o)

5SGXEA7K2F40C2N鑵冲嵃

5SGXEA7K2F40C2N鑵冲嵃

5sgxea7k2f40c2n鎺ㄨ枽渚涙噳(y墨ng)鍟� 鏇村>

  • 鐢�(ch菐n)鍝佸瀷铏�(h脿o)
  • 渚涙噳(y墨ng)鍟�
  • 鏁�(sh霉)閲�
  • 寤犲晢
  • 灏佽/鎵硅櫉(h脿o)
  • 瑭㈠児(ji脿)

5sgxea7k2f40c2n鍦栫墖

5sgxea7k2f40c2n