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鎻忚堪	闆嗘垚闆昏矾FPGA 336 I/O 672FBGA
鍒嗛	闆嗘垚闆昏矾(IC)锛屽祵鍏ュ紡-FPGA(鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄ｅ垪)
鍒堕€犲晢	鑻辩壒鐖�
绯诲垪	Cyclone?VE
鎵撳寘	鎵樼洡
闆朵欢鐙€鎱�(t脿i)	娲绘€�
闆诲-闆绘簮	1.07V?1.13V
宸ヤ綔婧害	0掳C?85掳C(TJ)
鍖呰/绠�	672-BGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏寘瑁�	672-FBGA(27x27)
鍩烘湰闆朵欢铏�	5CEFA9

鐢�(ch菐n)鍝佸湒鐗�

5CEFA9F27C8N

瑕�(gu墨)鏍煎弮鏁�(sh霉)

鍙法绋嬮倧杓鍨�	鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄ｅ垪
绗﹀悎REACH	鏄�
绗﹀悎姝愮洘RoHS	鏄�
鐙€鎱�(t脿i)	杞�(zhu菐n)绉�
绺絉AM浣�	14251008
JESD-30浠ｇ⒓	S-PBGA-B672
杓稿叆鏁�(sh霉)閲�	336.0
閭忚集鍠厓鏁�(sh霉)	301000.0
杓稿嚭鏁�(sh霉)閲�	336.0
绔瓙鏁�(sh霉)	672
鏈€浣庡伐浣滄韩搴�	0鈩�
鏈€楂樺伐浣滄韩搴�	85鈩�
闆绘簮	1.1,1.2 / 3.3,2.5
璩囨牸鐙€鎱�(t脿i)	涓嶅悎鏍�
搴ч珮	2.0姣背
瀛愰鍒�	鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄ｅ垪
闆绘簮闆诲妯�(bi膩o)绋�	1.1浼�
鏈€灏忎緵闆婚浕澹�	1.07浼�
鏈€澶ч浕婧愰浕澹�	1.13浼�
瀹夎椤炲瀷	琛ㄩ潰璨艰
鎶€琛�(sh霉)	CMOS
婧害绛夌礆	鍏朵粬
绲傜琛ㄦ牸	鐞�
绔瓙闁撹窛	1.0姣背
绲傜浣嶇疆	搴曢儴
闀峰害	27.0姣背
瀵害	27.0姣背
鍖呰涓婚珨鏉愭枡	濉戞枡/鐠�(hu谩n)姘фü鑴�
鍖呰浠ｇ⒓	BGA
鍖呰绛夋晥浠ｇ⒓	BGA672,26X26,40
鍖呰褰㈢媭	寤ｅ牬
鍖呰褰㈠紡	缍�(w菐ng)鏍奸櫍鍒�
鍒堕€犲晢鍖呰瑾槑	绗﹀悎RoHS妯�(bi膩o)婧�(zh菙n)锛孎(xi脿n)BGA-672

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鐒￠墰鐙€鎱�(t脿i)/RoHS鐙€鎱�(t脿i)	鐒￠墰/绗﹀悎RoHS
姘村垎鏁忔劅鎬ф按骞�(MSL)	3(168灏忔檪(sh铆))

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