鏅傞枔锛�2023/8/1 11:21:02
闁辫畝锛�632
鐢�(ch菐n)鍝佸瀷铏� | 5AGTFC7H3F35I3N |
鎻忚堪 | 闆嗘垚闆昏矾FPGA 544 I/O 1152FBGA |
鍒嗛 | 闆嗘垚闆昏矾(IC)锛屽祵鍏ュ紡-FPGA(鐝�(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪) |
鍒堕�犲晢 | 鑻辩壒鐖� |
绯诲垪 | Arria V GT |
鎵撳寘 | 鎵樼洡 |
闆朵欢鐙�鎱�(t脿i) | 閬庢檪鐨� |
闆诲-闆绘簮 | 1.12V?1.18V |
宸ヤ綔婧害 | -40掳C?100掳C(TJ) |
鍖呰/绠� | 1152-BBGA锛孎(xi脿n)CBGA瑁搁湶鐒婄洡 |
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏寘瑁� | 1152-FBGA(35x35) |
鍩烘湰闆朵欢铏� | 5AGTFC7 |
5AGTFC7H3F35I3N
鍙法绋嬮倧杓鍨� | 鐝�(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪 |
绗﹀悎REACH | 鏄� |
绗﹀悎姝愮洘RoHS | 鏄� |
鐙�鎱�(t脿i) | 杞�(zhu菐n)绉� |
鏈�澶ф檪閻橀牷鐜� | 670.0鍏嗚但 |
JESD-30浠ｇ⒓ | S-PBGA-B1152 |
JESD-609浠ｇ⒓ | 1铏� |
绺絉AM浣� | 15470592 |
杓稿叆鏁�(sh霉)閲� | 544.0 |
閭忚集鍠厓鏁�(sh霉) | 242000.0 |
杓稿嚭鏁�(sh霉)閲� | 544.0 |
绔瓙鏁�(sh霉) | 1152 |
宄板�煎洖娴佹韩搴�(鈩�) | 鏈(bi膩o)鏄� |
闆绘簮 | 1.15,1.2 / 3.3,2.5 |
璩囨牸鐙�鎱�(t脿i) | 涓嶅悎鏍� |
搴ч珮 | 2.7姣背 |
瀛愰鍒� | 鐝�(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪 |
闆绘簮闆诲妯�(bi膩o)绋� | 1.15浼� |
鏈�灏忎緵闆婚浕澹� | 1.12浼� |
鏈�澶ч浕婧愰浕澹� | 1.18浼� |
瀹夎椤炲瀷 | 琛ㄩ潰璨艰 |
鎶�琛�(sh霉) | CMOS |
绲傜瀹屾垚 | 閷�/閵�/閵�(Sn / Ag / Cu) |
绲傜琛ㄦ牸 | 鐞� |
绔瓙闁撹窛 | 1.0姣背 |
绲傜浣嶇疆 | 搴曢儴 |
鏅傞枔@宄板�煎洖娴佹韩搴︽渶澶у��(绉�) | 鏈(bi膩o)鏄� |
闀峰害 | 35.0姣背 |
瀵害 | 35.0姣背 |
鍖呰涓婚珨鏉愭枡 | 濉戞枡/鐠�(hu谩n)姘фü鑴� |
鍖呰浠ｇ⒓ | BGA |
鍖呰绛夋晥浠ｇ⒓ | BGA1152,34X34,40 |
鍖呰褰㈢媭 | 寤ｅ牬 |
鍖呰褰㈠紡 | 缍�(w菐ng)鏍奸櫍鍒� |
鍒堕�犲晢鍖呰瑾槑 | 绗﹀悎RoHS妯�(bi膩o)婧�(zh菙n)锛孎(xi脿n)BGA-1152 |
鐒￠墰鐙�鎱�(t脿i)/ RoHS鐙�鎱�(t脿i) | 鐒￠墰/绗﹀悎RoHS |
姘村垎鏁忔劅鎬ф按骞�(MSL) | 3(168灏忔檪) |
?鎶�琛�(sh霉)
?鑷虹⿳闆荤殑28绱嶇背鍒剁▼鎶�琛�(sh霉)
鈥擜rria V GX锛孏T锛孲X鍜孲T 鈥� 28绱嶇背浣庡姛鑰�(28LP)宸ヨ棟
鈥擜rria V GZ鈥�28绱嶇背楂樻�ц兘(28HP)宸ヨ棟
?鍚岄鐢�(ch菐n)鍝佷腑鏈�浣庣殑闈滄厠(t脿i)鍔熺巼(鍦ㄥ吀鍨嬫浠朵笅锛屽湪85掳C绲�(ji茅)鏅�锛屽皪浜�500K閭忚集鍏冧欢(LE)鑰岃█锛屽皬浜�1.2 W)
?0.85 V锛�1.1 V鎴�1.15 V鍏�(n猫i)鏍告(bi膩o)绋遍浕澹�
? 鎵撳寘
?鐔卞京(f霉)鍚堝�掕鑺墖BGA灏佽
?鍏锋湁鐩稿悓灏佽灏哄鐨勫绋ō(sh猫)鍌欏瘑搴�锛屽彲鍦ㄤ笉鍚岃ō(sh猫)鍌欏瘑搴︿箣闁撶劇绺伔绉�
?鍚墰锛岀劇閴�(鐒￠墰)鍜岀鍚圧oHS鐨勯伕浠�
?楂樻�ц兘FPGA鏋舵(g貌u)
?鍏锋湁鍥涘�嬪瘎瀛樺櫒鐨勫寮峰瀷8杓稿叆ALM
?鏀归�茬殑璺敱鏋舵(g貌u)鍙笡灏戞搧濉炲苟绺煭绶ㄨ 鏅傞枔
?鍏�(n猫i)閮ㄥ瓨鍎插
?M10K-鍏锋湁杌熼尟瑾ゆ牎姝ｇ⒓(ECC)鐨�10鍗�(Kb)鍏�(n猫i)瀛樺( 鍍呴檺Arria V GX锛孏T锛孲X鍜孲T瑷�(sh猫)鍌�)
?M20K-鍏锋湁纭珽CC鐨�20-Kb鍏�(n猫i)瀛樺(鍍匒rria V GZ瑷�(sh猫)鍌�)
?瀛樺劜鍣ㄩ倧杓櫍鍒楁ā濉�(MLAB)-640浣嶅垎甯冨紡LUTRAM锛屾偍鍙互鍦ㄥ叾涓� 浣跨敤澶氶仈50%鐨凙LM浣滅偤MLAB瀛樺劜鍣�
?宓屽叆寮忕‖鏍窱P濉�
?鍙畩绮惧害DSP
鈥斿師鐢熸敮鎸佸閬斿洓鍊嬩俊铏熻檿鐞嗙簿搴︾瓑绱�
-鍦ㄥ悓涓�鍙畩绮惧害DSP妯″涓�锛屼笁鍊�9 x 9锛屽叐鍊�18 x 18鎴栦竴鍊�27 x 27涔樻硶鍣�
-浣跨敤鍏╁�嬪彲璁婄簿搴SP妯″鐨勪竴鍊�36 x 36涔樻硶鍣�(鍍匒rria V GZ鍣ㄤ欢)
鈥旂敤浜庤剤鍕曟湁闄愯剤娌栭熆鎳�(y墨ng)(FIR)鐨�64浣嶇疮鍔犲櫒鍜岀礆鑱�(li谩n)
鈥斿祵鍏ュ紡鍏�(n猫i)閮ㄧ郴鏁�(sh霉)瀛樺劜鍣�
鈥旈爯(y霉)鍔犲櫒/娓涙硶鍣�锛屼互鎻愰珮鏁堢巼
? 鍏�(n猫i)瀛樻帶鍒跺櫒(鍍呴檺Arria V GX锛孏T锛孲X鍜孲T)
鈥擠DR3鍜孌DR2
?宓屽叆寮忔敹鐧�(f膩)鍣↖ / O
鈥旇嚜瀹氱京瀵︽柦
-Arria V GX鍜孲X瑷�(sh猫)鍌�-鏈�楂�6.5536 Gbps
-Arria V GT鍜孲T瑷�(sh猫)鍌�-鏈�楂�10.3125 Gbps
-Arria V GZ瑷�(sh猫)鍌�-楂橀仈12.5 Gbps
鈥� PCIExpress?(PCIe?)Gen2(x1锛寈2鎴杧4)鍜孏en1(x1锛寈2锛寈4鎴杧8)纭� IP锛屽叿鏈夊鍔熻兘鏀寔锛岀榛炲拰鏍圭鍙�
鈥� PCIe Gen3(x1锛寈2锛寈4鎴杧8)鏀寔(鍍呴檺Arria V GZ)
鈥� Gbps浠ュお缍�(w菐ng)(GbE)鍜孹AUI鐗╃悊绶ㄧ⒓瀛愬堡(PCS)
鈥旈�氱敤鍏叡鐒＄窔闆绘帴鍙�(CPRI)PCS
鈥斿崈鍏嗙礆鐒℃簮鍏夌恫(w菐ng)绲�(lu貌)(GPON)PCS
鈥� 10 Gbps浠ュお缍�(w菐ng)(10GbE)PCS(鍍匒rria V GZ)
鈥斾覆琛孯apidIO?(SRIO)PCS
鈥斿洜鐗规媺鑲疨CS(鍍匒rria V GZ)
?鏅傞悩缍�(w菐ng)绲�(lu貌)
?楂橀仈650 MHz鐨勫叏鐞冩檪閻樼恫(w菐ng)绲�(lu貌)
?鍏ㄥ眬锛岃薄闄愬拰澶栧湇鏅傞悩缍�(w菐ng)绲�(lu貌)
?鍙互闂�(gu膩n)闁夋湭浣跨敤鐨勬檪閻樼恫(w菐ng)绲�(lu貌)浠ラ檷浣庡嫊鎱�(t脿i)鍔熻��
?閹栫浉鐠�(hu谩n)(PLL)
?楂樺垎杈ㄧ巼灏忔暩(sh霉)鍒嗛牷PLL
?绮剧⒑鐨勬檪閻樺悎鎴�锛屾檪閻樺欢閬茶鍎熷拰闆跺欢閬茬珐娌� (ZDB)
?鏁存暩(sh霉)妯″紡鍜屽皬鏁�(sh霉)妯″紡
?LC鎸暕鍣ˋTX鐧�(f膩)閫佸櫒PLL(鍍匒rria V GZ)
?FPGA閫氱敤I / O (GPIO)
?1.6 Gbps LVDS鎺ユ敹鍣ㄥ拰鐧�(f膩)閫佸櫒
?800 MHz / 1.6 Gbps澶栭儴瀛樺劜鍣ㄦ帴鍙�
?鐗囧収(n猫i)鍖归厤(OCT)
?3.3 V鏀寔
?澶栭儴瀛樺劜鍣ㄦ帴鍙�
? 浣庡欢閬茬殑鍏�(n猫i)瀛樻帴鍙�
鈥旂‖鐩ゆ帶鍒跺櫒-鏈�楂�1.066 Gbps
鈥旇粺瀛樺劜鎺у埗鍣�-鏈�楂�1.6 Gbps
? 浣庡姛鑰楅珮閫熶覆琛屾帴鍙�
?600 Mbps鑷�12.5 Gbps闆嗘垚鏀剁櫦(f膩)鍣ㄩ�熷害
?6 Gbps鏅傛瘡鍊嬮�氶亾灏忎簬105 mW锛�10 Gbps鏅傛瘡鍊嬮�氶亾灏忎簬165 mW锛�12.5 Gbps鏅傛瘡鍊嬮�氶亾灏忎簬170 mW
?鐧�(f膩)閫侀爯(y霉)鍔犻噸鍜屾帴鏀舵鍧囪
?鍊嬪垾閫氶亾鐨勫嫊鎱�(t脿i)閮ㄥ垎閲嶆柊閰嶇疆
?甯舵湁鏀寔9.8304 Gbps CPRI鐨勮粺PCS鐨勭墿鐞嗕粙璩�(zh矛)闄勪欢(PMA)(鍍呴檺Arria V GT鍜孲T)
?鍏锋湁鏀寔楂橀仈9.8 Gbps CPRI鐨勭‖PCS鐨凱MA(鍍匒rria V GZ)
?鏀寔10GBASE-R鍜�10GBASE-KR鐨勭‖PCS(鍍匒rria V GZ)
? HPS (鍍呴檺Arria V SX鍜孲T 瑷�(sh猫)鍌�)
?闆欐牳ARM Cortex-A9 MPCore铏曠悊鍣�-鏈�楂橀牷鐜囬珮閬�1.05 GHz锛屽苟鏀寔灏嶇ū鍜岄潪灏嶇ū澶氳檿鐞�
?鎺ュ彛澶栧湇瑷�(sh猫)鍌欌�� 10/100/1000浠ュお缍�(w菐ng)濯掗珨瑷晱鎺у埗(EMAC)锛孶SB 2.0 On-The-GO(OTG)鎺у埗鍣�锛屽洓璺覆琛屽鍦嶈ō(sh猫)鍌欐帴鍙�(QSPI)闁冨瓨鎺у埗鍣紝NAND闁冨瓨鎺у埗鍣�锛屽畨鍏ㄦ暩(sh霉)瀛�/澶氬獟楂斿崱(SD / MMC)鎺у埗鍣紝UART锛屼覆琛屽鍦嶈ō(sh猫)鍌欐帴鍙�(SPI)锛孖2C鎺ュ彛鍜屽閬�85鍊婬PS GPIO鎺ュ彛
?绯荤当(t菕ng)澶栧湇瑷�(sh猫)鍌�-閫氱敤瀹氭檪鍣�锛岀湅闁�鐙楀畾鏅傚櫒锛岀洿鎺ュ瓨鍎插櫒瑷晱(DMA)鎺у埗鍣�锛孎(xi脿n)PGA閰嶇疆绠＄悊鍣ㄥ拰鏅傞悩 鍜岄噸缃鐞嗗櫒
?鐗囦笂RAM鍜屽紩灏�(d菐o)ROM
?HPS-FPGA姗嬫帴鍣�-鍖呮嫭FPGA鍒癏PS锛孒PS鍒癋PGA鍜岃紩閲忕礆鐨� HPS鍒癋PGA姗嬫帴鍣�锛岄�欎簺姗嬫帴鍣ㄥ厑瑷盕PGA绲�(ji茅)妲�(g貌u)鐧�(f膩)甯冧氦鏄撳埌HPS涓殑寰炵珯锛屽弽涔嬩害鐒�
? FPGA鍒癏PS SDRAM鎺у埗鍣ㄥ瓙绯荤当(t菕ng)鈥旀彁渚涜垏HPS SDRAM鎺у埗鍣ㄧ殑澶氱鍙ｅ墠绔�(MPFE)鐨勫彲閰嶇疆鎺ュ彛
? ARM CoreSight?JTAG瑾�(di脿o)瑭﹁í鍟忕鍙�锛岃窡韫ょ鍙ｅ拰鐗囦笂璺熻工瀛樺劜
?閰嶇疆
?闃茬鏀瑰叏闈㈢殑瑷�(sh猫)瑷堜繚璀�锛屽彲淇濊鎮ㄥ璨寸殑IP鎶曡硣
?澧炲挤鐨勯珮绱氬姞瀵嗘(bi膩o)婧�(zh菙n)(AES)瑷�(sh猫)瑷堝畨鍏ㄥ姛鑳�
?CvP
?FPGA鐨勯儴鍒嗗拰鍕曟厠(t脿i)閲嶆柊閰嶇疆
?鏈夋簮涓茶(AS)x1鍜寈4锛岀劇婧愪覆琛�(PS)锛孞TAG鍜屽揩閫熺劇婧愬苟琛�(FPP)x8锛寈16鍜寈32(Arria V GZ)閰嶇疆閬搁爡
?閬�(yu菐n)绋嬬郴绲�(t菕ng)鍗囩礆
5AGTFC7H3F35I3N绗﹁櫉
5AGTFC7H3F35I3N鑵冲嵃
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