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銆�銆�浠�4 閬�1 澶氳矾寰�(f霉)鐢ㄥ櫒鐐轰緥锛�
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity MUX4_1 is
    Port ( c0 : in  STD_LOGIC;
           c1 : in  STD_LOGIC;
           c2 : in  STD_LOGIC;
           c3 : in  STD_LOGIC;
           s : in  STD_LOGIC_VECTOR (1 downto 0);
           z : out  STD_LOGIC);
end MUX4_1;
architecture Behavioral of MUX4_1 is
begin
     process(s)          --if 瑾�(y菙)鍙ユ弿杩�
     begin
      if(s="00") then z<=c0;
      elsif(s="01") then z<=c1;
      elsif(s="10") then z<=c2;
      else  z<=c3;
      end if;
    end process;
  --process(s)            --case 瑾�(y菙)鍙ユ弿杩�
--begin
--   case s is
--       when "00" =>z<=c0;
--      when "01" =>z<=c1;
--      when "10" =>z<=c2;
--      when others =>z<=c3;
--  end case;
--end process;
end Behavioral;